Sun Mar 06, 2016 10:00 am
pi@raspberrypi:~ $ dmesg |grep spi
[ 11.008964] spi spi0.0: setting up native-CS0 as GPIO 8
[ 11.009269] spi spi0.1: setting up native-CS1 as GPIO 7
Nothing doesn`t change, not getting bit timing error.
pi@raspberrypi:~ $ sudo vcdbg log msg |& grep -v -E "(HDMI|gpioman)"
000698.991: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
000699.028: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
000699.067: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
000699.103: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
000699.144: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
000699.177: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
000711.884: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
000711.918: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
000880.221: clock: Set PLLB_VCO to 640000000
000880.332: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
000880.367: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 0.000000
000880.404: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 1.000000
000880.436: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 0.000000
000880.462: clock: Set PLLB_VCO to 640000000
000880.569: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
000880.598: clock: Set PLLB_VCO to 1200000000
000880.671: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
000897.765: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 0.000000
000902.525: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
000902.563: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
000902.601: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
000902.637: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
000902.679: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
000902.710: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
000915.499: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
000915.530: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
000915.628: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
000915.665: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
000915.702: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
000915.736: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
000915.777: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
000915.810: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
000928.563: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
000928.595: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
000928.726: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
000928.760: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
000928.799: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
000928.835: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
000928.874: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
000928.905: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
000929.094: clock: Set PLLH_VCO to 864000000
000929.258: clock: clock_set_clock: dst: CLK_VEC, source: PLLH_AUX, div: 2.000000
000929.628: clock: clock_set_clock: dst: CLK_TSENS, source: XOSC, div: 9.600000
000929.697: *** Restart logging
000930.615: Read command line from file 'cmdline.txt'
dwc_otg.lpm_enable=0 console=ttyAMA0,115200 console=tty1 root=/dev/mmcblk0p2 rootfstype=ext4 elevator=deadline fsck.repair=yes rootwait
000930.821: clock: clock_set_clock: dst: CLK_UART, source: PLLD_PER, div: 166.666700
000931.439: Loading 'kernel.img' from SD card
001163.963: Kernel trailer DTOK property says yes
001164.078: Loading 'bcm2708-rpi-b.dtb' from SD card
001197.331: dtparam: uart0_clkrate=3000000
001203.919: dtparam: audio=on
001215.573: Loaded overlay 'mcp2515-can0'
001215.592: dtparam: oscillator=8000000
001216.159: dtparam: interrupt=25
001263.678: dtparam: arm_freq=700000000
001265.159: Unknown dtparam 'arm_freq' - ignored
001265.189: dtparam: core_freq=250000000
001270.399: dtparam: cache_line_size=32
001280.179: clock: Set PLLB_VCO to 1400000000
001280.297: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001280.378: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
001280.438: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
001280.509: clock: Set PLLA_VCO to 2000000000
001280.615: clock: clock_set_clock: dst: CLK_V3D, source: PLLA_CORE, div: 4.000000
001280.677: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
001280.740: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
001281.685: clock: Set PLLB_VCO to 640000000
001281.758: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001281.787: clock: Set PLLB_VCO to 1400000000
001281.860: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001281.898: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 1.000000
001281.934: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 0.000000
001281.961: clock: Set PLLB_VCO to 1400000000
001282.077: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
002866.602: vchiq_core: vchiq_init_state: slot_zero = 0x5b880000, is_master = 1