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DavidS
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Re: Complete ARM only Instruction Set (as promissed).

Sun Dec 02, 2018 11:27 pm

Heater wrote:
Sun Dec 02, 2018 11:13 pm
DavidS,
I would have thought that ARM wold have stuck a little closer to an ARM like ISA.
Why?

The move from 32 to 64 bits is a big one. Requiring a lot of compiler and tools development and so on. It's a good opportunity to ditch all the junk you have been hoarding for years that never turned out to be useful. Perhaps adopt some new techniques.

Same happened with the move from Intel's 32 bit architecture to AMD's 64.
And your example does not work. The AMD64 archetechure is a lot closer to the IA32 arc, and the AMD64 ISA has the same instrucion encodings for many instructions. Not to mention that the AMD64 ISA is capable of running IA32 code while in long mode, without the hoops that are needed for running traditional ARM code in AARCH64 mode.

While I dislike IA32 and AMD64 (having coded for it enough) I have to give credit to the fact that the transistion to AMD64 did not break everything (it only broke 16-bit stuff, and not baddly).

Though I have to give ARM credit in that they have clearely defined that AARCH32 is here to stay on AARCH64 processors, as that is part of the AARCH64 specification. Unfortunately if I want to run AARCH32 code in a AARCH64 environment I have to get the OS to switch the entire systems out of AARCH64 (not very easy BTW) run the code (with inturupts dissabled, or using speciall AARCH32 handlers) switch back into AARCH64 so that the rest of the system can run. That is not a good design, not when you have a stockpile of original software (much of which is still perfectly safe) dating back 30+ years, much of which the original source has long since been lost (and remakes almost neaver live up to the originals).
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DavidS
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Re: Complete ARM only Instruction Set (as promissed).

Sun Dec 02, 2018 11:47 pm

@Heater:

Ok now you have gone and done it :) . I have a bit of nostalgia to play in x86 assembly (yuck), so I opened up DOSBox and am installing an old OS on it (a couple years old, FreeDOS 1.1) and am going to get NASM setup and going to write a 'simple' toy game. Just going to have to create a v86 environment to be able to call the OS, after I setup a usable GDT, LDT, IDT, and TSS and Page table, enable A20 (thought the keyboard controller of all things), enable PMODE with the code already in memory, get the address of the Vesa 2.0 LFB, set the video mode by calling to realmode interupt through the v86 environment, and then can start into the game.

Any one that thinks getting out of hypervisor is difficult, I challenge to write a full PMODE game for MS-DOS/DR-DOS/PC-DOS/FreeDOS without using a premade DPMI. Just getting a completely usable PMODE environment setup and working is more work than writing an entire (even monolithic) OS kernel for the ARM. Oh yea on the x86 you have to get into PMODE to setup Long mode if anyone is wondering about that.
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Paeryn
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 12:02 am

DavidS wrote:
Sun Dec 02, 2018 8:55 pm
Paeryn wrote:
Sun Dec 02, 2018 6:15 pm
The DSP related instructions, (S|SH|Q|U|UHS|UQ)(ADD|SUB)(16|8), (also ASX|SAX with the same type prefixes but no size suffix as they are halfword only). These were from before NEON and work on the ARM registers.
Thank you for that. All of it I was not thinking about the sync instructions. I did not include the hypervisor only stuff on purpose.
So going by your own definition of ARM instructions you deliberately left some out, therefore you didn't fulfil what you originally said
...I would prove how small the ARM instruction set is by posting the entire ARM opcodes...
DavidS wrote:
Sun Dec 02, 2018 8:55 pm
Though the 8-bit ADD and such are there, look at the bits for data processing instructions.
Except I specifically said the DSP related instructions, that is QADD8, SADD8 etc. (I put the brackets to show the instruction name is made from exactly one of each bracket group - although the size is actually optional for xADD/xSUB, not giving a size means a single 32bit operation) which are not represented in your list. Using your lists would put QADD8 R0, R1, R2 in the LDR/STR section (where you only list how bits 11-0 are decoded for an immediate offset and not how they are used for a register offset). The nearest would be (I think) STRT R0, [R1], -R2, LSL #31 although there is one bit different (bit 4) which makes it a QADD8 rather than an STRT. Just checking... <Edit, I was trying STRBT which has two bits different (being byte rather than word), having the T after the size qualifier confused me>.

Code: Select all

   0:   e6210f82        strt   r0, [r1], -r2, lsl #31
   4:   e6210f92        qadd8   r0, r1, r2

Code: Select all

QADD8
Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range
–2**7 ≤ x ≤ 2**7 – 1, and writes the results to the destination register.
Last edited by Paeryn on Mon Dec 03, 2018 12:17 am, edited 1 time in total.
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DavidS
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 12:06 am

Paeryn wrote:
Mon Dec 03, 2018 12:02 am
DavidS wrote:
Sun Dec 02, 2018 8:55 pm
Paeryn wrote:
Sun Dec 02, 2018 6:15 pm
The DSP related instructions, (S|SH|Q|U|UHS|UQ)(ADD|SUB)(16|8), (also ASX|SAX with the same type prefixes but no size suffix as they are halfword only). These were from before NEON and work on the ARM registers.
Thank you for that. All of it I was not thinking about the sync instructions. I did not include the hypervisor only stuff on purpose.
So going by your own definition of ARM instructions you deliberately left some out, therefore you didn't fulfil what you originally said
Not dilibrately, I already said thank you for pointing out what I missed.

The only op I intentionally left out is SWP. I am attempting to write an update to the OP on this thread to include the ops I forgot about. I have no idea how you got that impression.
...I would prove how small the ARM instruction set is by posting the entire ARM opcodes...
DavidS wrote:
Sun Dec 02, 2018 8:55 pm
Though the 8-bit ADD and such are there, look at the bits for data processing instructions.
Except I specifically said the DSP related instructions, that is QADD8, SADD8 etc. (I put the brackets to show the instruction name is made from exactly one of each bracket group - although the size is actually optional for xADD/xSUB, not giving a size means a single 32bit operation) which are not represented in your list. Using your lists would put QADD8 R0, R1, R2 in the LDR/STR section (where you only list how bits 11-0 are decoded for an immediate offset and not how they are used for a register offset). The nearest would be (I think) STRBT R0, [R1], -R2, LSL #31 although there are two bits different (bits 4 and 22) which makes it a QADD8 rather than an STRBT. Just checking...

Code: Select all

   0:   e6610f82        strbt   r0, [r1], -r2, lsl #31
   4:   e6210f92        qadd8   r0, r1, r2

Code: Select all

QADD8
Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range
–2**7 ≤ x ≤ 2**7 – 1, and writes the results to the destination register.
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Paeryn
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 12:57 am

DavidS wrote:
Mon Dec 03, 2018 12:06 am
Not dilibrately, I already said thank you for pointing out what I missed.

The only op I intentionally left out is SWP. I am attempting to write an update to the OP on this thread to include the ops I forgot about. I have no idea how you got that impression.
Perhaps from the last sentence here...
DavidS wrote:
Sun Dec 02, 2018 8:55 pm
Thank you for that. All of it I was not thinking about the sync instructions. I did not include the hypervisor only stuff on purpose.
I don't believe that you deliberately left out all the others (there are more, I just listed the ones off the top of my head). The only hypervisor related instruction I listed is HVC I think, a few others are privileged but that's no reason to avoid listing them, they are still valid instructions and very important ones.

Just looking at the ArmARM, you listed bits 27-26 as 01 meaning Load/Store instructions whereas ARM says bits 27-25 = 010 are Load/Store as are bits 27-25 = 011 so long as bit 4 is 0, if bit 4 is 1 then the 011 instructions are the Media instructions (what I listed as DSP-related).
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 1:24 am

Paeryn wrote:
Mon Dec 03, 2018 12:57 am
DavidS wrote:
Mon Dec 03, 2018 12:06 am
Not dilibrately, I already said thank you for pointing out what I missed.

The only op I intentionally left out is SWP. I am attempting to write an update to the OP on this thread to include the ops I forgot about. I have no idea how you got that impression.
Perhaps from the last sentence here...
DavidS wrote:
Sun Dec 02, 2018 8:55 pm
Thank you for that. All of it I was not thinking about the sync instructions. I did not include the hypervisor only stuff on purpose.
I don't believe that you deliberately left out all the others (there are more, I just listed the ones off the top of my head). The only hypervisor related instruction I listed is HVC I think, a few others are privileged but that's no reason to avoid listing them, they are still valid instructions and very important ones.

Just looking at the ArmARM, you listed bits 27-26 as 01 meaning Load/Store instructions whereas ARM says bits 27-25 = 010 are Load/Store as are bits 27-25 = 011 so long as bit 4 is 0, if bit 4 is 1 then the 011 instructions are the Media instructions (what I listed as DSP-related).
Ok fair on that. The hypervisor stuff is now technically part of ARM. When I made the promise the ARMv8 did not exist, and I had not encountered an ARMv7 that comes up in hypervisor yet.

I will also include the hypervisor stuff.

I will double check on the load/store instructions, I may have made an error in entry.
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 1:46 am

Paeryn wrote:
Mon Dec 03, 2018 12:57 am
Just looking at the ArmARM, you listed bits 27-26 as 01 meaning Load/Store instructions whereas ARM says bits 27-25 = 010 are Load/Store as are bits 27-25 = 011 so long as bit 4 is 0, if bit 4 is 1 then the 011 instructions are the Media instructions (what I listed as DSP-related).
You are incorrect about that being incorrect. Note the value of bit 25 for Load/store immediate offset and for Load/store register ofset in this table from the ARM ARM:

Image

You will notice that bits 26-27 are 01, and bit 25 is the difference between immediate and register offset, exactly as I have it. Though you made me look to double check.

I am in the process of extending the original post to include the omitions, though I am not finding some of them in the ARM ARM (any version I have).

I will continue to leave out only SWP because it is depricated.
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 1:54 am

Paeryn wrote:
Mon Dec 03, 2018 12:02 am

Code: Select all

   0:   e6210f82        strt   r0, [r1], -r2, lsl #31
   4:   e6210f92        qadd8   r0, r1, r2
your opcodes are printed big-endian?
as -anl -EL prints:

Code: Select all

   820F21E6   strt    r0, [r1], -r2, lsl #31
   920F21E6   qadd8   r0, r1, r2

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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 2:29 am

WOW, thank you. I have been off by a bit behind without knowing it. I have a lot of the newer stuff in my quick documents, though I had always skimmed past the ARM instructions for parallel and saturating integer math, as I had thought from there mnemonics they were VFP/NEON (which I look up in my NEON references), now that I see they are indeed ARM instructions having bits 27-25 = 0b101 and bit 4 set to 1 (bit four differs them from a LDR/STR using a register offset), I realize I had overlooked something good.
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 2:52 am

Looks like I am not qualified to finish out the table. It is interesting I thought I knew the new ops, though because the way the ARM ARM lists these as undefined area, and requires looking at a section seperate than the rest of the instruction set I had overlooked all the DSP ops as ARM. I thought they were alternate names for some VFP/NEON op when I have seen them, though this does explain why I could never figure out what they were in normal VFP/NEON syntax.

So I will finish out most of what I missed other than the DSP stuff. Though I am going to have to learn the DSP stuff to make sure I get the discriptions correct. I can deal with the MMU, ARM, NEON, and even a small amount of stuff on the VideoCoreIV, though this one snuck up on me.
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 3:37 am

Would Arm chips be cheaper if the ARMv8/Aarch64 versions dropped all the 32bit instructions?
Pure 64bit opcodes and smaller dies sizes?
Are ARMs microcoded?
I think being RISC they are not?

The opcodes for A64 excluding T32/A32 would be smaller?
Would the A64 opcodes fit on one of those old plastic opcode sheets we all used instead of manuals.

My 3A+s just arrived and with Gentoo64 running on 3B+s I now have development systems for native embedded A64 coding.
Lots of the Arm manuals compare A64 to A32 and include T32/A32 stuff.
I just want to focus on pure 64bit as I don't expect I have enough neurons or time left learn everything in the A53's SOCs.
I have no interest in backwards compatibility.
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DavidS
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Re: Complete ARM only Instruction Set (as promissed).

Mon Dec 03, 2018 4:04 am

Gavinmc42 wrote:
Mon Dec 03, 2018 3:37 am
Would Arm chips be cheaper if the ARMv8/Aarch64 versions dropped all the 32bit instructions?
Pure 64bit opcodes and smaller dies sizes?
Are ARMs microcoded?
NO.
I think being RISC they are not?

The opcodes for A64 excluding T32/A32 would be smaller?
Would the A64 opcodes fit on one of those old plastic opcode sheets we all used instead of manuals.
No, though the basic ARMv6 opcodes will (plus the divide ops of ARMv7 and the new hyp and svc mode stuff). ARMv8 is huge in its instruction set. It is not very ARM like from my view. Put simply the AARCH32 opcodes would fit no problem on one of the old style opcode cards, the AARCH64 there is no chance unless you go under 1 point text size.
My 3A+s just arrived and with Gentoo64 running on 3B+s I now have development systems for native embedded A64 coding.
Lots of the Arm manuals compare A64 to A32 and include T32/A32 stuff.
I just want to focus on pure 64bit as I don't expect I have enough neurons or time left learn everything in the A53's SOCs.
I have no interest in backwards compatibility.
What about forwards compatibility? The AARCH64 is fairly new in the game, while the 32-bit ARM has been around for 35 years. Probability is that the 32-bit older ISA is going to be here for a long time to come, the 64-bit is still yet unproven as far as being able to make it long term on the market.

Point is you should look at both ISA's if you are woried about the future, and likely a few others. There are a few Open Source CPU projects I am following, that seem quite interesting in there potential for the future (two of which are ARM implementations). RISC V is interesting, though not to my liking. Then there are two different projects to use a subset of the old 680x0 ISA to create a new RISC ISA (that is using a fixed length subset where all instructions are exactly 16 bits, though a compatible subset), then there are some others of interesting for there similarity to early MIPS (that is never flusing the pipeline, always executing a few ops after a branch because they are already in the pipeline before the branch is executed).

So I hope you enjoy playing with the AARCH64, I will stick with ARM for the time being.
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