I've done this circuit diagram and I was hoping you could check a few resistor/capacitor values that I'm not sure about. If you could also explain how/why you choose any of these values as well I would be very grateful.
(Apologies about the size, there are limitations on what the forum will let me upload. You'll have to zoom in on it to make anything out)
The chip is a package with 2 4-stage shift registers in it (CD4015BE if you're interested), hence the two reset pins. Both are active high and they require 100ns being high to reset the chip. I've pulled the reset pins to +5V with a 10nF capacitor, and to ground with a 10k resistor so that the chip resets at power on. Are these values ok?
I'm also not sure about the resistors clamping the bases of the NPN and PNP transistors to ground and high, respectively. I've used 100k because I've been told it should be an order of magnitude greater than the current limiting resistor on the base, but this seems a bit high. Thoughts?
Finally, I'm switching my data and clock lines using transistors because the chip uses 5V logic. I have a resistor tying these lines to +5V, and then when I want them low, I make the bases of the transistors high, thus tying the lines to ground. Those pull up resistors are 100k. Is that again too big?
Thanks for any help