willyvmm
Posts: 6
Joined: Thu Dec 27, 2012 5:33 pm

GPIO FIQ interrupts possible?

Thu Dec 27, 2012 6:04 pm

Hi.
I need to handle ca. 2-3M external interrupts per second, and read data from GPIO.
Is it possible to extermally trigger the FIQ interrupts, or there is only possible to trigger IRQ's externally ?

willyvmm
Posts: 6
Joined: Thu Dec 27, 2012 5:33 pm

Re: GPIO FIQ interrupts possible?

Sat Dec 29, 2012 10:52 am

I could not find any solution how to throw FIQ externally ... but I think i found a solution. (It's not tested, that is only a concept).

- Configure irq on GPIO
- In IRQ handler, first of all check if this is MY - external interrupt, If Yes, switch processor into FIQ mode (It gives acces to banked r8-r12 registers !) , Read GPIO, store into memory, exit FIQ processor mode, clear interrupt flag, exit IRQ.
- If that is not MY interrupt, call standard IRQ handler with nested IRQ's enabled.

Do you think is that the correct way to fast handling external IRQ's ?

tufty
Posts: 1456
Joined: Sun Sep 11, 2011 2:32 pm

Re: GPIO FIQ interrupts possible?

Sat Dec 29, 2012 12:04 pm

No. That's not even close.

You can only have one FIQ handler, it's triggered by the interrupt controller itself.

You enable FIQ and *disable IRQ* for the interrupt source you want, enable FIQ globally (cpsie f), and you should get FIQs for your interrupt source, which will drop direct into the FIQ handler.

willyvmm
Posts: 6
Joined: Thu Dec 27, 2012 5:33 pm

Re: GPIO FIQ interrupts possible?

Sat Dec 29, 2012 12:14 pm

BCM2835-ARM-Peripherals page 115 - i know that...
But please tell me HOW to configure processor to throw FIQ externally ...

Page 116 says:

FIQ Source.
The FIQ source values 0-63 correspond to the GPU interrupt table. (See above)
The following values can be used to route ARM specific interrupts to the FIQ vector/routine:

FIQ index Source
0-63 GPU Interrupts (See GPU IRQ table)
64 ARM Timer interrupt
65 ARM Mailbox interrupt
66 ARM Doorbell 0 interrupt
67 ARM Doorbell 1 interrupt
68 GPU0 Halted interrupt (Or GPU1)
69 GPU1 Halted interrupt
70 Illegal access type-1 interrupt
71 Illegal access type-0 interrupt
72-127 Do Not Use

There is nothing about external source :(

So my idea is a workarround to lack of external FIQ.

tufty
Posts: 1456
Joined: Sun Sep 11, 2011 2:32 pm

Re: GPIO FIQ interrupts possible?

Sat Dec 29, 2012 4:28 pm

If you can handle a GPIO interrupt using an IRQ, you should be able to do so using an FIQ. So if you're routing your gpio interrupts through, eg, GPU interrupt 49 (GPIO[0]), you should set the FIQ source to 49. However, that limits you to interrupts on events on one bank of GPIOs. It's probably more useful to disable IRQs on GPIO[0-3] and set the FIQ source to GPIO[3] (GPU interrupt 52), which should give you an interrupt on very GPIO event, on any bank. You'll then have to disambiguate between banks, of course, using GPEDS0 and GPEDS1.

That's my reading of things, anyhow. I've not used the GPIO interrupts, so I can't be sure.

willyvmm
Posts: 6
Joined: Thu Dec 27, 2012 5:33 pm

Re: GPIO FIQ interrupts possible?

Sat Dec 29, 2012 8:02 pm

Thanks.
That make sense, I have read the manual once again, and found the point.

I will test that soon (I'am on holidays now), and let you know.

dwelch67
Posts: 961
Joined: Sat May 26, 2012 5:32 pm

Re: GPIO FIQ interrupts possible?

Sat Dec 29, 2012 8:23 pm

Technically speaking, if you read the TRM for the ARM1176blahsomething, there are separate nIRQ and nFIQ signals into the core. So it is "possible" that a vendor does not have everything tied to the IRQ also tied to the FIQ. I dont use FIQ much but seem to remember any time I have it has always been an option either IRQ or FIQ (meaning the vendor had tied them together). We dont have visibility into the broadcom design, and unfortunately the docs are pretty bad, so hacking is involved. Personally I would enable all the interrupts in the interrupt controller (but not enable interrupts in the arm) then poll the interrupt status register(s) and change the state of the gpio pin (well configure it, in theory, to create an interrupt). This will give you the interrupt number and verify that it actually can deliver an interrupt to the interrupt controller. From there it is a simple matter of enabling the interrupt, by number, into the fiq then enabling the fiq interrupt in the ARM and providing a handler.

The point I really wanted to make though is that if you look at the manuals that are available (ARM1176 TRM) it is "possible" that a vendor can make a product where the IRQ and FIQ are not tied together and you would then be limited in software to only using the one provided.

David

gsh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
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Joined: Sat Sep 10, 2011 11:43 am

Re: GPIO FIQ interrupts possible?

Sat Dec 29, 2012 9:48 pm

We are already using the fiq to do USB interrupt.

Check out drivers/USB/host/dwc-otg/dwc-otg-hcd-intr.c

Or search in that dir for fiq

Gordon
--
Gordon Hollingworth PhD
Raspberry Pi - Director of Software Engineering

dwelch67
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Re: GPIO FIQ interrupts possible?

Sun Dec 30, 2012 2:54 am

dwelch67 wrote:Technically speaking, if you read the TRM for the ARM1176blahsomething, there are separate nIRQ and nFIQ signals into the core. So it is "possible" that a vendor does not have everything tied to the IRQ also tied to the FIQ. I dont use FIQ much but seem to remember any time I have it has always been an option either IRQ or FIQ (meaning the vendor had tied them together). We dont have visibility into the broadcom design, and unfortunately the docs are pretty bad, so hacking is involved. Personally I would enable all the interrupts in the interrupt controller (but not enable interrupts in the arm) then poll the interrupt status register(s) and change the state of the gpio pin (well configure it, in theory, to create an interrupt). This will give you the interrupt number and verify that it actually can deliver an interrupt to the interrupt controller. From there it is a simple matter of enabling the interrupt, by number, into the fiq then enabling the fiq interrupt in the ARM and providing a handler.

The point I really wanted to make though is that if you look at the manuals that are available (ARM1176 TRM) it is "possible" that a vendor can make a product where the IRQ and FIQ are not tied together and you would then be limited in software to only using the one provided.

David
duh, that was pretty stupid, they have to be separate...

David

willyvmm
Posts: 6
Joined: Thu Dec 27, 2012 5:33 pm

Re: GPIO FIQ interrupts possible?

Fri Feb 08, 2013 9:15 pm

Finally I can confirm, GPIO can throwr FIQ but ...
The **** architecture, GPU over CPU is not suitable to handle interrupts at that rate. It is possible to handle interrupts at rate ca 3,5 MHz, but ... its not reliable. Too many dropped interrupts - too many dropped data.

gertk
Posts: 52
Joined: Mon Aug 29, 2011 9:08 am

Re: GPIO FIQ interrupts possible?

Sun Jun 09, 2013 11:11 am

willyvmm wrote:Finally I can confirm, GPIO can throwr FIQ but ...
The **** architecture, GPU over CPU is not suitable to handle interrupts at that rate. It is possible to handle interrupts at rate ca 3,5 MHz, but ... its not reliable. Too many dropped interrupts - too many dropped data.
I am contemplating a similar construct, although at 1 MHz (bus snoop) where the handler must run withing 500 ns reading three bytes from a multiplexed bus and (eventually) respond with a read/write of data to/from internal memory.
In the manual I read that it is possible to setup a special piece of memory (TCM) which is not bothered by cache and such. Maybe that can make things work ? Or DMA possibly ?

JacobL
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Re: GPIO FIQ interrupts possible?

Mon Jun 10, 2013 3:20 pm

gertk wrote:Or DMA possibly ?
DMA will not work at that rate. DMA operations typically take 10s of us just for starting and stopping. DMA is normally only good for one thing: letting the CPU do other stuff while large blocks of data is transferring in the background, at the price of increased latency.

I'm not sure what the TCM refers to, but I think it should be possible to disable some/all cache and use internal SRAM. Usually data and instructions are in separate blocks here so watch out.

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joan
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Location: UK

Re: GPIO FIQ interrupts possible?

Mon Jun 10, 2013 3:52 pm

JacobL wrote:
gertk wrote:Or DMA possibly ?
DMA will not work at that rate. DMA operations typically take 10s of us just for starting and stopping. DMA is normally only good for one thing: letting the CPU do other stuff while large blocks of data is transferring in the background, at the price of increased latency.

I'm not sure what the TCM refers to, but I think it should be possible to disable some/all cache and use internal SRAM. Usually data and instructions are in separate blocks here so watch out.
I'm using Linux/C to sample gpios 0-31 at 1MHz, using DMA to pace the samples. I don't possess the means to check the accuracy. When I also drive servos at the same time I have noticed servo jitter if the network is also busy. I'd be fairly confident there is a stable solution in bare metal.

http://www.raspberrypi.org/phpBB3/viewt ... 30#p347830

willyvmm
Posts: 6
Joined: Thu Dec 27, 2012 5:33 pm

Re: GPIO FIQ interrupts possible?

Mon Jun 10, 2013 3:55 pm

Thanks GERTk for the tip.
I have missed this feature and I would say it could be possible using TCM (@JacobL TCM - Tight Coupled Memory).
The window can be 64kB wide, so thats enought.
But ..
I dropped that idea because of too much complicated glue logic arround.
Instead of i moved project into FPGA :D

dwelch67
Posts: 961
Joined: Sat May 26, 2012 5:32 pm

Re: GPIO FIQ interrupts possible?

Tue Jun 11, 2013 12:36 am

JacobL wrote:
gertk wrote:Or DMA possibly ?
DMA will not work at that rate. DMA operations typically take 10s of us just for starting and stopping. DMA is normally only good for one thing: letting the CPU do other stuff while large blocks of data is transferring in the background, at the price of increased latency.
A side note:

Some systems the DMA takes over the bus such that the CPU is halted and cant do anything else. Saves on the programmer writing code but isnt necessarily faster. Some that are in parallel have slow dma that only steals one out of so many cycles to keep the cpu from stopping all together, but that means it overall takes more time than if you had just done it with the cpu instructions directly. You really have to know your system to know if DMA buys you anything, sometimes it is great, sometimes it is worse...I generally avoid it so I dont know how this processor works have not played with it. This processor does strongly appear to have a shared memory system between the gpu and the ARM and I would assume the GPU wins all performance battles over that memory and whatever else is going on behind the curtain (whatever mmu if any they have over there, caching, etc). If you are looking for arm performance you might want to try another system. If you are wanting a low cost system, good enough speed, good enough graphics, etc, the Raspberry Pi is worth evaluating.

FIQ buys you a few clock cycles in pushing and popping some registers over a normal IRQ. If your code is compiled and not in asm, and other factors you probably wont notice the difference between FIQ and IRQ, you might find much better performance gains elsewhere. Just trying to measure the difference on this system involves shared with the gpu resources which are non-deterministic as we dont have enough info. I wouldnt be surprised and this is maybe what you already found is that you might do okay most of the time but occasionally the arm may get delayed while the gpu does something, you might have one out of X accesses to something take significantly longer than the rest.

David

JacobL
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Re: GPIO FIQ interrupts possible?

Wed Jun 12, 2013 3:31 pm

joan wrote: I'm using Linux/C to sample gpios 0-31 at 1MHz, using DMA to pace the samples. I don't possess the means to check the accuracy. When I also drive servos at the same time I have noticed servo jitter if the network is also busy. I'd be fairly confident there is a stable solution in bare metal.

http://www.raspberrypi.org/phpBB3/viewt ... 30#p347830
I had a quick look at your post. It looks like you are doing exactly what DMA is good at. You set it up once, and then let DMA do the grunt work of repeatedly reading/writing data. If I understand gertk's case correctly, then he will need to reconfigure DMA every time inside his 500ns window.

gertk
Posts: 52
Joined: Mon Aug 29, 2011 9:08 am

Re: GPIO FIQ interrupts possible?

Wed Jun 12, 2013 4:40 pm

Biggest problem I have now is that I want to read a 16 bit address bus, an 8 bit data bus and the control signals (phase 2 clock) and R/W all through the few IO pins available.

Effectively the Pi will be interrupted each phase 2 clock signal...

I have found some DIP packaged bus buffers (74AHC244) which can be powered from the Pi side and accept 5 Volt signals on the inputs.

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