I'd like to implement a per CPU core one-shot timer. I usually good at interpreting docs, but this time I'm really stuck. I'm trying to use the ARM Generic Timer.
First, I can confirm that exceptions are set up correctly (I'm at EL1, VBAR, SPSel etc. selects the handler correctly). According to the ARM-Cortex-A53-Manual section 10.2, Non-Secure EL1 physical timer is implemented. The DDI0487D document on page D10-2653 says this about the timer:
And then the description of CNTP_CTL_EL0 says:The CompareValue View of a timer operates as a 64-bit upcounter. The timer condition is met when the appropirate counter reaches the value programmed into its CompareValue register. When the timer condition is met, an interrupt is generated if the interrupt is not masked in the corresponding register, CNTP_CTL_EL0, CNTHP_CTL_EL2, CNTPS_CTL_EL1, CNTV_CTL_EL0, the asserted interrupt is the same as the interrupt asserted by the Non-Secure instance of AArch32 register CNTP_CTL.
This sounds great, exatly what I want. I initialize it as:ISTATUS, bit  The status of the timer. This bit indicates whether the timer condition is met: 0 Timer condition is not met. 1 Timer condition is met. When the value of ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
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CNTHCTL_EL2 |= 3 CNTKCTL_EL1 = 0 CNTHP_CTL_EL2 = 1 CNTP_CTL_EL0 = 3 // IMASK=1, ENABLE=1 DAIFCLR = 1
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CNTP_CVAL_EL0 = CNTPCT_EL0 + CNTFRQ_EL0 CNTP_CTL_EL0 = 1 // IMASK=0, ENABLE=1
Another loosely related question, why are there so many timer devices?
- BCM2837 page 172 System Timer: this is clear, ARM independent, but therefore unfortunately not per CPU core configurable.
- BCM2837 page 196 Timer (ARM side): base addres 0x3F00B400 is this the same as the ARM Timer in the IC?
- BCM2836 QA7 specifies ARM control at 0x40000000 has two ARM timers: page 9 Core timer register and page 17 Local timer. What are those? Are they the same as the ARM Generic Timer or totally separate? How are they relate to the Timer (ARM side) at B400 and the ARM Timer bit in the IC?