The response in depending on your context.
There are 4 sys timers defined. For each of them you have the registers : CS, CLO, CHI, and c0--c3 attached to system timer 0-3.
Each timer is connected to an interrupt, for PI 2 interrupt 0-3.
You have to follow this steps :
- select a timer (ex T1)
- enable the selected timer in the CS register (01 correspond to timer 1)
- set the free run counter (CLO, CHI) 64 bit Low, High.(depends on your application)
- reset timer match (write 01 in the CS register)
- clear the pending interrupt (IRQ pending 1, bit 1)
- enable the interrupt 1 corresponding to SYS_TIMER_1
You are now ready to receive the interrupts :
- in the IRQ routine :
- check the interrupt pending bit for t1 (interrupt controller)
- if it is set :
- check register CS bit 1 for t1 interrupt
- if is set :
- do your action (so fast you can do, because the interrupts are disabled)
- set again the CLO, CHI counter
- clear pending interrupt for t1 (c1)
- clear the pending interrupt 1 (interrupt controller)
- restore saved registers
- exit IRQ mode and restore the original core mode.
If you need the more information or code example, let me know !