To carry out hardware cache maintenance one needs to use the Snoop Control Unit (SCU) on the CortexA53. To access these signals, they are physical pins on the SoC (such as BROADCASTCACHEMAINT ).
Is there any way via some mailbox interface to the GPU carry out such hardware cache maintenance operations?
Does the GPU_NO_CACHE (0xc0000000) ored with a virtual address actually control these pins? ie the last 2 bits?