jamesmintram
Posts: 31
Joined: Mon Jan 15, 2018 12:14 am

UART and Caching

Sun Sep 30, 2018 3:57 pm

So, today I have enabled the cache and what I receive over UART when testing on device is garbage.

UART works fine when caching is disabled
Everything works - even with caching enabled - when running in Qemu

The only thing that appears to go wrong when running it on a Pi3 with caching enabled is my UART
output is a garbled mess. (The amount of garbage is proportional to the amount I try to send over UART)

Anyone have any idea what could be causing this?
Anyway of figuring out where it is going wrong? (I have tried a lot of stuff)

As a test, I tried enabling caching in this demo: https://github.com/bztsrc/raspi3-tutori ... tualmemory and did not see any output. Does it work for anyone else? (I use that as an example as my page tables + system registers are setup in an almost identical way)

LdB
Posts: 1102
Joined: Wed Dec 07, 2016 2:29 pm

Re: UART and Caching

Sun Sep 30, 2018 5:21 pm

I had issues with the code as well.

At a guess, you are getting garbage with your code because the baud rate is wrong.
I am guessing the baudrate is wrong because you use the mailbox message to change the clock and it's failing because of cache coherency issues.

You can
1.) do all the mailbox calls before you turn the cache on
OR
2.) On your mailbox write routine where you are passing an address to the structure (lets call it called addr) then try
__asm volatile ("dc civac, %0" : : "r" (addr) : "memory");
Before you send the address to the GPU taking the data at the address to coherency.

I will leave you to lookup what it does.
http://infocenter.arm.com/help/index.js ... JDBHI.html
We all went thru this with various messages with the mailbox message going to the GPU when the cache is on and the GPU seeing different data in the structure because of the cache.

jamesmintram
Posts: 31
Joined: Mon Jan 15, 2018 12:14 am

Re: UART and Caching

Sun Sep 30, 2018 5:45 pm

Ah yes, that makes perfect sense. Easy to forget that the Mailbox is an "external" device.

Just a thought... I wonder if you set your memory flags to outer shareable and the cache to Write Through - whether that would work without cache cleaning? (Ensuring correct use of memory barriers)..

Anyway, I will look at adding some cache cleaning. Thanks!

jamesmintram
Posts: 31
Joined: Mon Jan 15, 2018 12:14 am

Re: UART and Caching

Sun Sep 30, 2018 7:30 pm

Boom.. worked first time!

Thanks :)

sheroy
Posts: 47
Joined: Fri Jun 14, 2013 5:34 pm

Re: UART and Caching

Wed Nov 21, 2018 10:40 pm

This Helped me too for AARCH32!!

I just had enabled MMU and caches, the code worked perfectly with either the data cache disabled or the MMU disabled. It did not work when both were enabled.
In the code I was writing to the mailbox repeatedly to read the core temperature via the mailbox interface. Only the first call worked all others were failing showing a core temperature of 0! I Struggled thinking it was a problem of memory barriers and tried working on it without success!


I added the line, where va is the virtual address of the mailbox message after which a mailbox Read and write was carried out.

Code: Select all

 uint32_t va = (uint32_t)&mailbox_message;
 asm volatile ("MCR p15, 0, %0, c7, c14, 1" : : "r" (va) : "memory");
 mailbox_write(  MAILBOX_TAGS_ARM_TO_VC , (uint32_t) &mailbox_message | GPU_NOCACHE);
  mailbox_read(   MAILBOX_TAGS_ARM_TO_VC );
 
It Worked!

More info can be found
http://infocenter.arm.com/help/index.js ... GBCHB.html
and the cortex A53 manual

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