The other timers that the QA7 document refers to are the Generic Timers which are per core, you can find some information in this post viewtopic.php?t=135121&p=922616 about how to use them.timanu90 wrote:By the document QA7 this seems to be possible but, I don't understand how that timer works
Have a look at this document (page 109). The base address of the interrupt controller on the RPi 2 is 0x3F00B000. You have to check the 3 pending registers to know, which interrupt(s) is/are pending.timanu90 wrote:I can't find a way to know wich interrupt fired. For example if I have uart and timer irq how i can know which one am I servicing?
I was thinking on something similar to that. But i already tested and I have a problem. The IRQ pending registers on interrupt controller after the interrupt started seems to be cleared by hardware. First thing I am doing is read the 3 register (0x3f00b000, 0x3f00b004, 0x3f00b008) at the start of irq_handler all return 0. (checked twice for errors hope I am not wrong xD).This can be simple, e.g. take the first interrupt source by number which is pending, and then the next, and so on until all pending interrupt sources have been handled.
Oops. When I wrote the base address of the interrupt controller is 0x3F00B000, I had the register list on page 112 of that Peripherals document in mind, where is defined:timanu90 wrote:First thing I am doing is read the 3 register (0x3f00b000, 0x3f00b004, 0x3f00b008) at the start of irq_handler all return 0. (checked twice for errors hope I am not wrong xD).
The Pi system has two independent sets of interrupts.I am going to try enable the mini uart rx interrupt and see what it reports.
So it is working now. That's good. I wouldn't care about that mailbox interrupt status. I think nobody is using these BCM2835 mailboxes with interrupts in bare metal programming.timanu90 wrote:I managed to enable the mini uart interrupts and is like I said in last post. Only the mail boxes I can't get the status.
I don't find it "strange". I think its design is the logical consequence of the requirement to be compatible with the previous RPi models.It's quite a strange interrupt controller xD. But it is what we have.