I'm working on a fast IO interface using the GPIO pins to send and receive data from an FPGA. The code is written in C and uses direct GPIO register read and writes based on code found here:
I use 16 pins for data (GPIO 0 - 15) and a few for hansdshake.
The Pi seems to able to output data via the GPIOpins (writing to the output set and clear registers) much faster than it can input data by reading the level registers.
I've modified my hardware data transfer protocol to cope with this, and sending data from the FPGA to the Pi I can achieve a pretty respectable 23.4 Mbyte/s.
Reading data is not so good, since every read of the GPIO pin level register seems to stall until 528ns has elapsed since the previous read - this is about 32 cycles of the IO clock (which may or may not be significant).
So I'm limited to an input rate of about 7.57 Mbyte/s.
I'd like to know if this is what should be expected (with some more knowledge of exactly how the IO hardware works than is avaialble to me), and if there is anything that can be done to speed things up. (if that 'stall' time could be reduced to half I'd be pretty happy !).
If anyone feels they can help out I'm happy to post whatever bits of code or logic analyser traces would help. I haven't done so yet because I'm not quite sure if I'm asking in the right place.