technix
Posts: 120
Joined: Sat Jul 13, 2013 4:55 pm

Suggestion: high speed pin multiplexeres

Mon Dec 03, 2018 12:00 pm

This is an idea I have been cooking for a while, intended for the next revision of the SoC. The high speed pin multiplexer allows switching several high speed signal pins around, making room for additional features and redefinition of some I/O pins without sacrificing compatibility. Older software is not aware of any additional hardware, including the multiplexers, so 100% downward compatibility is guaranteed through the default reset state of the multiplexers which retains existing connections and behavior; while newer software can remap the pins and load the drivers for the new hardware, unleashing the full potential of the chip.

1. USB multiplexers, making room for a full XHCI USB 3.0 host controller. The USB multiplexer set would involve two multiplexers with a shared select input signal: one 3PDT and one 6PDT. The 3PDT mux determines where the USB lines of the onboard dwc_otg controller, the existing USB controller of the Pi, goes: the 6PDT multiplexer when the select bit is reset, or a second set of USB pins that goes to the power jack if set. The 6PDT mux determines where the main USB lines, now 6 instead of 2 allowing for full USB 3.0, connects to: the 3PDT mux if reset, or a new XHCI controller if set. When the select signal is reset the USB pins are connected to the existing dwc_otg controller and the power jack does not have a working USB connection, retaining the exact behavior of the current chips; when the remap bit is set in the software, the existing dwc_otg is disconnected from the main USB port and connected to the power connector, and the main USB port is connected to a new XHCI controller, enabling the new behavior and full USB 3.0 support.

2. MIPI multiplexers, making room for a PCIe x2 root complex. The MIPI multiplexer include four 6PDT multiplexers and a decoder, allowing up to one of the MIPI CSI or DSI ports to be repurposed into a PCIe x2 or PCIe x1 interface. For the existing Pi boards, this means that you can get a PCIe x1 port from either the DSI ir the CSI connector. For older software none of the multiplexers are changed to the PCIe mode, retaining existing behavior; with newer software the PCIe root complex can be initialized and one of the channels can be switched into PCIe mode, allowing the connection of some advanced hardware like PCIe SSD, hardware RAID cards, or even graphics cards.

jamesh
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Re: Suggestion: high speed pin multiplexeres

Mon Dec 03, 2018 2:48 pm

Please stop posting "What I think should be in the next Pi" threads.

The next Pi is already designed, the SoC was speced two years ago. Even the next next Pi feature set is defined.

We do know what we are doing. Most of the the time.
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technix
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Joined: Sat Jul 13, 2013 4:55 pm

Re: Suggestion: high speed pin multiplexeres

Mon Dec 03, 2018 4:33 pm

jamesh wrote:
Mon Dec 03, 2018 2:48 pm
Please stop posting "What I think should be in the next Pi" threads.

The next Pi is already designed, the SoC was speced two years ago. Even the next next Pi feature set is defined.

We do know what we are doing. Most of the the time.
What I am hoping for is that this kind of idea can enter the pipeline regardless when or if it would come into a product. You do understand that for a while you guys had no competition, and then people discovered certain shortcomings like restricted RAM and lack of any kind of general purpose interface faster than 500Mbps, and now you got a lot of competitions right? The whole idea of adding those high speed pin mux is to allow almost arbitrary future feature expansions with zero risk of breaking compatibility even with kernels (but not GPU code) released back from the release day of the original Pi. This way you can break free of that "no compatibility break" rule and replace peripheral blocks entirely with next to zero restriction on IP selection, as long as the original peripheral is kept in place and the pin mux default to the old peripheral.

fruitoftheloom
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Re: Suggestion: high speed pin multiplexeres

Mon Dec 03, 2018 4:56 pm

technix wrote:
Mon Dec 03, 2018 4:33 pm
jamesh wrote:
Mon Dec 03, 2018 2:48 pm
Please stop posting "What I think should be in the next Pi" threads.

The next Pi is already designed, the SoC was speced two years ago. Even the next next Pi feature set is defined.

We do know what we are doing. Most of the the time.
What I am hoping for is that this kind of idea can enter the pipeline regardless when or if it would come into a product. You do understand that for a while you guys had no competition, and then people discovered certain shortcomings like restricted RAM and lack of any kind of general purpose interface faster than 500Mbps, and now you got a lot of competitions right? The whole idea of adding those high speed pin mux is to allow almost arbitrary future feature expansions with zero risk of breaking compatibility even with kernels (but not GPU code) released back from the release day of the original Pi. This way you can break free of that "no compatibility break" rule and replace peripheral blocks entirely with next to zero restriction on IP selection, as long as the original peripheral is kept in place and the pin mux default to the old peripheral.

What part of future product road map already decided by RPT do you not comprehend.

You appear to not have heed the above advice !
Retired disgracefully.....

jamesh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
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Re: Suggestion: high speed pin multiplexeres

Mon Dec 03, 2018 9:06 pm

technix wrote:
Mon Dec 03, 2018 4:33 pm
jamesh wrote:
Mon Dec 03, 2018 2:48 pm
Please stop posting "What I think should be in the next Pi" threads.

The next Pi is already designed, the SoC was speced two years ago. Even the next next Pi feature set is defined.

We do know what we are doing. Most of the the time.
What I am hoping for is that this kind of idea can enter the pipeline regardless when or if it would come into a product. You do understand that for a while you guys had no competition, and then people discovered certain shortcomings like restricted RAM and lack of any kind of general purpose interface faster than 500Mbps, and now you got a lot of competitions right?
No, it never occured to us. Oh, hold on, yes it did.
technix wrote:
Mon Dec 03, 2018 4:33 pm
The whole idea of adding those high speed pin mux is to allow almost arbitrary future feature expansions with zero risk of breaking compatibility even with kernels (but not GPU code) released back from the release day of the original Pi. This way you can break free of that "no compatibility break" rule and replace peripheral blocks entirely with next to zero restriction on IP selection, as long as the original peripheral is kept in place and the pin mux default to the old peripheral.
There are better ways of achieving all these things, which we are well aware of and I won't be going in to.

You also need to be aware of the HUGE cost involved in designing silicon. Even minor changes to an SoC can cost $Millions, so even just bolting some high speed GPIO system on the side of the SoC is an expensive project.
Principal Software Engineer at Raspberry Pi (Trading) Ltd.
Contrary to popular belief, humorous signatures are allowed. Here's an example...
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