### Complete ARM only Instruction Set (as promissed).

Posted:

**Sun Dec 02, 2018 3:11 pm****ARM Instructions In a Couple Pages:**

Keeping a Promise:

In 2012 I had made a promise on these forums that one day I would prove how small the ARM instruction set is by posting the entire ARM opcodes on a space that could be printed in a couple of pages. This is me keeping that promise, which I had forgotten about for a while.

What Instructions Again:

These are the ARM instructions, that is none of the coprocessors, just the ARM ops. So NO VFP/NEON, etc, just the actuall ARM instructions (up to ARMv8 AARCH32, so only the real 32 bit mode ARM instructions).

Also this is only ARM, so

**No Thumb**

And this is an opcode reference, not a programmers manual.

The Opcodes:

**Start here:**

Data Processing Instructions take the form (all instructions are 32-bits wide):

Code: Select all

```
Bits | Meaning
-------+-------------------------------------------------------------------
31-28 | Condition code, only execute op if true:
| 0x0 = EQ If equal, zero flag set.
| 0x1 = NE If not equal, zero flag cleared.
| 0x2 = CS If carry flag set.
| 0x3 = CC If Carry flag cleared.
| 0x4 = MI Minus, negitive.
| 0x5 = PL Plus, positive.
| 0x6 = VS Overflow flag set.
| 0x7 = VC Overflow Flag cleared.
| 0x8 = HI Unsigned higher.
| 0x9 = LS Lower or Same, unsigned.
| 0xA = GE Greater than or equal, signed.
| 0xB = LT Less than, signed.
| 0xC = GT Greater or equal, signed.
| 0xD = LE Less than or equal, signed.
| 0xE = AL Always true, unconditional.
| 0xF = NV RESERVED, used to extend opcodes in later ARMs.
27-26 | Set to 0 for these instructions.
25 | Imediat Operand specifier (if 0 Opr2 is register with optional
| shift applied, if 1 Opr2 is imed val see below for format).
24-21 | Opcode:
| 0x0 = AND Bitwise AND.
| 0x1 = EOR Bitwise Exclusive OR.
| 0x2 = SUB Subtract.
| 0x3 = RSB Reverse subtract.
| 0x4 = ADD Add.
| 0x5 = ADC Add with carry.
| 0x6 = SBC Subtract with carry.
| 0x7 = RSC Reverse Subtract With Carry.
| 0x8 = TST TST bits.
| 0x9 = TEQ Test if equal.
| 0xA = CMP Compare.
| 0xB = CMN Compare negitive.
| 0xC = ORR Bitwise OR.
| 0xD = MOV Copy value.
| 0xE = BIC Bit Clear.
| 0xF = MVN Move negitive.
20 | S flag, if 1 condition codes are set based on operation, if 0
| condition codes disgarded.
19-16 | Rn, the first source register.
15-12 | Rd, the destination register.
11-0 | Operand 2 (Opr2). Can be immed or register depending on bit 25.
| If bit 25 is set this is an imediate operand and the format is:
| 8-11 = Shift amount.
| 0-7 = 8 Bit immediate value.
| If bit 25 is clear, it is a register value, with the form:
| 4-11 = Shift value.
| 0-3 = Register
```

Code: Select all

```
bit | Meaning
-------+--------------------------------------------------------------------
31-28 | Condition (same as above). If condition is 0xF and bit 24 clear
| Then this becomes BLX
27-25 | Constant 0b101.
24 | Link bit, if set branch with link, if clear just branch.
23-0 | Offset to branch.
```

Next up is Multiply and Multiply With Accumulate:

Code: Select all

```
bit | Meaning
-------+--------------------------------------------------------------------
31-28 | Condition, same as Data Processing.
27-24 | Constant 0b0000.
23 | Long, if set this is a long (64-bit dest) multiply.
22 | For Long Multiply only, U flag, set if unsigned, clear if signed.
21 | Accumulate, if set multiply with accumulate, if clear just multiply.
20 | S bit, if set condition codes are updated, otherwise discarded.
19-16 | Register for high word of dest.
15-12 | Register for low word of dest.
11-8 | source reg.
7-4 | Constant 0b1001.
3-0 | Multiplicand register.
```

Code: Select all

```
BIT | Meaning
-------+--------------------------------------------------------------------
31-28 | Condition same as data processing.
27-26 | Constant 0b01.
25 | Imediate specifier.
24 | Post Indexed if clear, pre indexed if set.
23 | Up/Down bit, offset added if set, offset subtracted if clear.
22 | If clear word transfer, if set byte transfer.
21 | If set the final used address is written into the base address.
20 | If set this is a load, if clear it is a store.
19-16 | Base register.
15-12 | Destination Register.
11-0 | Offset.
```

Code: Select all

```
BIT | Meaning
-------+--------------------------------------------------------------------
31-28 | Condition, same as data processing.
27-25 | Constant 0b100.
24-16 | Same meanings as LDR/STR.
15-0 | Register List. Where bit 0 set for R0, bit 2 R2 ... bit 15 R15.
```

0xYFVVVVVV

Where VVVVVVV is the number SWI is called with. The ARM ignores this number,

it is there for the operating system to determine the call. Y is the normal conditional feild same as other ops.

Coprocessor Data Transfer:

Code: Select all

```
BIT | Meaning
-------+--------------------------------------------------------------------
31-28 | Condition, same as data processing.
27-25 | Constant 0b110.
24 | Pre index if set, if clear post index.
23 | Up/Down bit, if set add offset, if clear subtract offset.
22 | Length of transfer.
21 | If set used address written to ARM base register.
20 | If set load from coprocessor, if clear store to coprocessor.
19-16 | ARM Base register.
15-12 | Coprocessor Register.
11-8 | Coprocessor number.
7-0 | Offset.
```

Code: Select all

```
BIT | Meaning
-------+--------------------------------------------------------------------
31-28 | Condition, same as data processing.
27-24 | Constant 0b1110
23-20 | Operation part 1 (Op1) code.
19-16 | Coprocessor register.
15-12 | Coprocessor destination reg/ ARM reg if bit 4 is set.
11-8 | Coprocessor number.
7-5 | Operation part 2 (Op2) code.
3-0 | Coprocessor register m.
```

**no**NEON, etc)

I omited the SWP instruction because it has become depricated.

Also I did not list the UDIV/SDIV instructions, these I can not find an accurate reference on and I do not use. Some references give one form and some another, and they conflict with each other, using the recommend mnemonic will not assemble, giving a format error (so I can not compare the generated opcode).

As stated above not going into any of the coprocessors here, only worried about the ARM. It is especially important to remember that many extensions are coprocessors now that many are a standard part of the chip. Knowing that they are indeed cooprocessors will help with optimization.