User avatar
adun
Posts: 102
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Location: Switzerland

Re: PiZero Ethernet pHAT

Sat Jan 16, 2016 3:12 pm

Thanks to clear this up. :) So without adding a mux for the data line this would not work.
Back to SPI1 solution.... :(
PS:
Perhaps it would be easier to use SPI1 for the light control so no specific driver is needed.

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karrika
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Location: Finland

Re: PiZero Ethernet pHAT

Sat Jan 16, 2016 3:53 pm

Actually no. The SPI1 solution is no longer interesting. There is no sensible use case in it as seen in my previous entry.

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adun
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Location: Switzerland

Re: PiZero Ethernet pHAT

Tue Feb 02, 2016 1:47 pm

Here is the DT overlay I've made to enable
SPI0 with additional CS on GPIO 5,6
SPI ethernet and PWM audio. So no longer wiring pi is needed to set PWM on GPIO 12,13.

GPIO 5: SPI0_CE3 unused
GPIO 6: SPI0_CE2 unused
GPIO 7: SPI0_CE1 unused
GPIO 8: SPI0_CE0 ENC28J60 CS
GPIO 9: SPI0_MISO
GPIO 10: SPI0_MOSI
GPIO 11: SPI0_SCLK
GPIO 12: PWM
GPIO 13: PWM
GPIO 25: ENC28J60 Reset


Put the code below in a file called miscap-overlay.dts and compile it using:

Code: Select all

sudo apt-get update
sudo apt-get install device-tree-compiler
dtc -@ -I dts -O dtb -o miscap-overlay.dtb miscap-overlay.dts
sudo cp miscap-overlay.dtb /boot/overlays
Then add "dtoverlay=miscap" to /boot/config.txt and reboot.

==================================================

Code: Select all

 
/*
Overlay for MisCap pHAT for the Microchip ENC28J60 Ethernet Controller
and 2-channel PWM Audio on GPIO 12,13
Enables SPI0 using spi-bcm2835 driver with additional CE3 on GPIO 5 and CE2 on GPIO 6
*/

/dts-v1/;
/plugin/;

/ {

compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";

/* SPI0 */
fragment@0 {
      target = <&gpio>;
      __overlay__ {
          spi0_pins: spi0_pins {
              brcm,pins = <7 8 9 10 11>;
              brcm,function = <4>; /* alt0 */
          };     
      };
   };

   fragment@1 {
      target = <&spi0>;
      __overlay__ {
         #address-cells = <1>;
         #size-cells = <0>;
         pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
         status = "okay";
         cs-gpios = <0>, <0>, <&gpio 6 1>, <&gpio 5 1>;
           
         /*The first two <0>s request that native CS's 0 and 1 are used
         (even though the driver will convert them to GPIO CS's),
         and GPIO's 6 and 5 are used as active-low chip selects 2 and 3. */

         spidev@0{
              compatible = "spidev";
              reg = <0>;	/* CE0 */
              #address-cells = <1>;
              #size-cells = <0>;
              spi-max-frequency = <500000>;
          };

          spidev@1{
              compatible = "spidev";
              reg = <1>;	/* CE1 */
              #address-cells = <1>;
              #size-cells = <0>;
              spi-max-frequency = <500000>;
          };
         
         spidev@2{
            compatible = "spidev";
            reg = <2>;   /* CE2 */
            #address-cells = <1>;
            #size-cells = <0>;
            spi-max-frequency = <500000>;
         };

         spidev@3{
            compatible = "spidev";
            reg = <3>;   /* CE3 */
            #address-cells = <1>;
            #size-cells = <0>;
            spi-max-frequency = <500000>;
         };
      };
   };

/*reserve the extra GPIO 5 and 6 so no other drivers can claim them + mark them as outputs */

   fragment@2 {
      target = <&gpio>;
      __overlay__ {
         spi0_cs_pins: spi0_cs_pins {
            brcm,pins = <5 6>;
            brcm,function = <1>; /* out */
         };
      };
   };
 
/* enc28j60 enthernet */
 
   fragment@3 {
      target = <&spi0>;
      __overlay__ {
         /* needed to avoid dtc warning */
         #address-cells = <1>;
         #size-cells = <0>;

         status = "okay";

         spidev@0{
            status = "disabled";
         };

         eth1: enc28j60@0{
            compatible = "microchip,enc28j60";
            reg = <0>; /* CE0 */
            pinctrl-names = "default";
            pinctrl-0 = <&eth1_pins>;
            interrupt-parent = <&gpio>;
            interrupts = <25 0x2>; /* falling edge */
            spi-max-frequency = <12000000>;
            status = "okay";
         };
      };
   };

   fragment@4 {
      target = <&gpio>;
      __overlay__ {
         eth1_pins: eth1_pins {
            brcm,pins = <25>;
            brcm,function = <0>; /* in */
            brcm,pull = <0>; /* none */
         };
      };
   };


/* PWM */

  fragment@5 {
      target = <&gpio>;
      __overlay__ {
         pwm_pins: pwm_pins {
            brcm,pins = <12 13>;
            brcm,function = <4 4>; /* Alt0 */
         };
      };
   };

   fragment@6 {
      target = <&pwm>;
      __overlay__ {
         pinctrl-names = "default";
         pinctrl-0 = <&pwm_pins>;
         status = "okay";
      };
   };


};
Last edited by adun on Tue Feb 16, 2016 8:39 pm, edited 16 times in total.

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karrika
Posts: 1070
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Location: Finland

Re: PiZero Ethernet pHAT

Tue Feb 02, 2016 2:56 pm

Thank you! I was just starting to Google what needs to be done for the audio bits. I have to download this and test it out. There is an eeprom on the board so I should be able to insert this code onto the chip. When the PiZero DeviceTree is fully operational the setup should be automatic.

About the future models I believe it may be a good idea to just expose the different CE0-CE2 signals and keep the bus at SPI0. Added 5V->3.3V could be good. Diode protections to audio pins.

And move the ENC module a little towards the 40 pin header.

Anything else?

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adun
Posts: 102
Joined: Fri Mar 20, 2015 9:25 am
Location: Switzerland

Re: PiZero Ethernet pHAT

Tue Feb 02, 2016 3:15 pm

Yes I think also those changes are good. We must only consider if we keep the ethernet on those pins or move it to other GPIOs for CE and/or reset. That would make it compatible with other SPI HATs , SPI display or SD1 SDIO devices etc. The miscap overlay could then easily be changed...

For the audio here are the B+ schematics where they use a driving buffer : https://learn.adafruit.com/introducing- ... io-outputs
Image

PS:
I updated my overlay above: Now the overlay should enable SPI by itself and for testing purpose I added additional chip select (GPIO-CS) where we can move the enc28j60 CS if needed.
GPIO 5: SPI0_CE3
GPIO 6: SPI0_CE2
For miscap SPI0 with additional CS could be exposed.

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karrika
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Location: Finland

Re: PiZero Ethernet pHAT

Fri Apr 08, 2016 7:01 pm

I just made my first eeprom test on Miscap. Only good news :D

The overlay created by adun can be added into the eeprom. This means that a stock Jessie image needs NO EDITING at all. No need for anything in /boot/config.txt.

Just power it on and Ethernet works over enc28j60. The audio is also automatically mapped to Miscap headphone socket.

I will post the code and instructions of how to update existing Miscap's during the weekend.

HAT's are amazing creatures. Miscap is actually HAT complient except for the form factor.

It is also nice to see that PiZero works together with HAT's just like the other Pi's.

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karrika
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Location: Finland

Re: Miscap - PiZero Ethernet pHAT

Sat Apr 09, 2016 1:07 pm

There is now a tutorial and instructions of how to program the eeprom on Miscap. Enjoy http://discohat.com/miscap/

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adun
Posts: 102
Joined: Fri Mar 20, 2015 9:25 am
Location: Switzerland

Re: Miscap - PiZero Ethernet pHAT

Sat Apr 09, 2016 9:03 pm

Nice to hear that everything is working ;)
The tutorial you made is very good, also for general information how HAT eeprom works.
If the additional SPI0 CS are no longer needed for the final version, I can remove them from the code as those were just for testing.

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DougieLawson
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Re: Miscap - PiZero Ethernet pHAT

Sun Apr 10, 2016 9:47 pm

The only thing I couldn't work out was whether

Code: Select all

dtparam=i2c_vc=on
can be removed from /boot/config.txt after the pHAT eeprom stuff is written.

I've currently got that left in and GPIO12 & 13 have the right status.
Note: Having anything humorous in your signature is completely banned on this forum. Wear a tin-foil hat and you'll get a ban.

Any DMs sent on Twitter will be answered next month.

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adun
Posts: 102
Joined: Fri Mar 20, 2015 9:25 am
Location: Switzerland

Re: Miscap - PiZero Ethernet pHAT

Sun Apr 10, 2016 11:00 pm

Code: Select all

dtparam=i2c_vc=on
is to get acces to i2c0 from userspace. This means that i2c0 is now controlled by ARM no longer by the GPU (firmware) as it usually is.
You can safely remove this line after the code is written to the eeprom.
The firmware loads the stuff from the eeprom during boot by muxing i2c0 to GPIO 0,1.
After that GPIO 0,1 are set as inputs.
But as the PiZero has no CSI/DSI there is no need that the GPU controlls i2c0. So if you let dtparam=i2c_vc=on you gain a second i2c bus.
Last edited by adun on Sun Apr 10, 2016 11:15 pm, edited 1 time in total.

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DougieLawson
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Re: Miscap - PiZero Ethernet pHAT

Sun Apr 10, 2016 11:08 pm

I did another reboot, my MAX7219 needed to move to SPI1 so I rewrote the eeprom (because when I read it back there was a byte missing), took the i2c_vc stuff out and it's still working.

Looks like I met a bug in the eepflash.sh stuff (and I can't be bothered to look deeper because it's working right now).
Note: Having anything humorous in your signature is completely banned on this forum. Wear a tin-foil hat and you'll get a ban.

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karrika
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Re: Miscap - PiZero Ethernet pHAT

Fri Aug 19, 2016 6:42 am

Stop the press - latest news.

The audio channels of Miscap are sometimes swapped.

If you use Miscap with a RPi2 or RPi3 everything is ok.

If you use it on a RPi1 or PiZero then the left and right channels are swapped.

There was also an error in setting up the audio pins for the latest firmware.

The correct way is:

Code: Select all

    /* Audio */

    fragment@5 {
      target = <&audio_pins>;
      __overlay__ {
        brcm,pins = <12 13>;
        brcm,function = <4>; /* alt0 */
      };
    };
The previous blob was connecting pwm outputs to the pins that happened to do the same thing. But this is the correct way. You need to have a very recent firmware for this to work.

I am still hoping for the talented guys behind the fimware to invent a patch by which the left and right channels would go to the same pins on all models.

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