sheroy
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Impedance of GPIO lines

Sat Oct 29, 2016 12:41 pm

What is the impedance of the GPIO lines/tracks on the raspberry pi 3 and other models?

Also does the SoC support digitally controlled impedance? What are the registers to tweak?

Further what is the best performance(in terms of the eye diagram) that can be obtained with the GPIO. What is the best termination to be used.


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jdb
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Re: Impedance of GPIO lines

Sat Oct 29, 2016 4:05 pm

The GPIO tracks routing to the pin header are not impedance-controlled or length-matched.

The GPIO drive has roughly equal rise/fall balance (but not guaranteed across process/temperature). The bulk drive strength can be adjusted in 8*2mA steps from 2mA to 16mA (approx). There are no facilities for precision impedance tuning.

Modest decoupling is provided for each GPIO electrical bank. The maximum useable I/O clock frequency on the GPIO pins is in the range 30-50MHz.
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sheroy
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Re: Impedance of GPIO lines

Tue Nov 08, 2016 1:05 pm

But what is the best impedance(on an average -- or as electrical engineers do by trial and error) to supply to the GPIO lines so that I can transfer data faster. I may be able to play with the drive strength to optimize the impedance of the source. I need to run the Sclk line at about 100 MHz... to achieve the required sampling rate..

Further, is it possible to obtain the schematics of the Pi3 so that the decoupling capacitors of each of the banks can be identified?

I was following the PI from the early days, I thought it was open schematics....but I do not see that direction(sorry).

Thanks.

andies
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Re: Impedance of GPIO lines

Sun Dec 18, 2016 4:27 pm

I did the following: I shortened GPIO27 to 3.3V using a resistor on a RPi3. Then I used a digital voltmeter to measure the voltage at this resistor (high impedance, BBC MA 5D). I had six resistors at hand and could measure the following voltage V depending on resistor R:

Code: Select all

resistor (kΩ)	voltage (V)
 0,468	0,03
   1,0	0,064
   1,5	0,095
    10	0,56
    15	0,78
    39	1,485
------------------
     ∞	  3,3 (no resistor)
Below is a graph of those data. Assuming there is a constant impedance and using the usual resistor-voltage ratio I get that the impedance of GPIO is between 47 and 51kΩ. On average it is 50kΩ.
impedance RPi GPIO.jpg
impedance RPi GPIO.jpg (52.14 KiB) Viewed 5537 times
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Burngate
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Re: Impedance of GPIO lines

Mon Dec 19, 2016 11:31 am

As far as I can see, and assuming GPIO-27 was set as an input for your tests, you've verified that the internal pull-down resistor is close to 50k.
Is that what you intended?

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Ronaldlees
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Re: Impedance of GPIO lines

Mon Dec 19, 2016 2:32 pm

Of course the impedance will vary with frequency. But I think 100 MHZ is too high to matter.
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andies
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Re: Impedance of GPIO lines

Tue Dec 20, 2016 12:59 pm

My measurements were without any frequencies.
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jdb
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Re: Impedance of GPIO lines

Wed Dec 21, 2016 9:17 pm

That measurement is invalid - the output driver static resistance is in the 10s of ohms range, not kilohms. The pull resistors are in the range of 20-60kohm so that tallies with what you've measured.

As a rule of thumb, series-terminating unidirectional GPIOs (i.e. ones driving clock or output data lines) with a 33 ohm resistor close to the GPIO ball gives reasonable matching to typical PCB traces. Reliable operation with a clock at 100MHz is probably beyond the scope of the GPIOs brought out to the 40-pin header simply because that sort of header isn't designed to carry signals at that frequency.

Adding additional decoupling would probably be wasted effort - it's the integrity of the signals as the propagate across the connector (and on the destination board) that would likely be the limiting factor.
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andies
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Re: Impedance of GPIO lines

Thu Dec 22, 2016 9:57 am

Burngate wrote:As far as I can see, and assuming GPIO-27 was set as an input for your tests, you've verified that the internal pull-down resistor is close to 50k.
Is that what you intended?
Yes.
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andies
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Re: Impedance of GPIO lines

Thu Dec 22, 2016 10:01 am

jdb wrote:That measurement is invalid
I am sorry, I do not know enough about electronics to understand what you wrote. I did not measure any clock, I was on GPIO 27 and this was set to input. Also, what is the connection of raspberry to printed circuit board (assuming that this stands for PCB)? I do not know how to deactivate the pull-down resistor, so I measured what I had at hand, etc.
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E3V3A
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Re: Impedance of GPIO lines

Thu Mar 16, 2017 4:02 am

Great question and lots of good info here. However, a correct and precise answer is still not seen.
jdb wrote:Reliable operation with a clock at 100MHz is probably beyond the scope of the GPIOs brought out to the 40-pin header simply because that sort of header isn't designed to carry signals at that frequency.
That can't be fully true. For example. many people use pifm to run GPIO up to 250 MHz in a very reliable way. Thus it is interesting to know what the resulting matching impedance at ~100 MHz should be.

jdb
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Re: Impedance of GPIO lines

Thu Mar 16, 2017 2:57 pm

Digital signal require well-defined edges (repeatable and "steep") for signal integrity. Background power supply or environmental electrical noise added to signals with poor edges corrupts data/clock signals due to slowly transitioning through the point at which the receiving device recognises a 1->0 or 0->1 transition. The lack of a sharp edge dramatically increases the chance that multiple transitions are detected or a transition is missed.

Blasting RF frequencies out of a GPIO and a hastily constructed antenna merely requires that there's some energy at the frequency of interest, which of course ignores the harmonic spray that pollutes far more spectrum than just the fundamental frequency.
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