I'm somewhat curious about why the referenced example is assumed to output a byte ten times, and not a 32-bit (4 byte) word. This whole part is not very clear at all in the published spec (especially whether the SPI0 can output any other bit length than 32bit, as the aux SPIs seem to be able to do), but the pertinent section referring to the SPI FIFO register says:
31:0 DATA - DMA Mode (DMAEN set)
If TA is clear, the first 32-bit write to this register
will control SPIDLEN and SPICS. Subsequent
reads and writes will be taken as four-byte data
words to be read/written to the FIFOs
Poll/Interrupt Mode (DMAEN clear, TA set)
Writes to the register write bytes to TX FIFO.
Reads from register read bytes from the RX
Granted, this seems to refer to the DMA mode, but no other mode is described there - does it work differently in non-DMA modes? Is there something we don't know (like what SPIDLEN / SPICS is, as they're not referred to anywhere else)?
I wrote some simple code where I tried to send a byte the the external PIC. I must admit that the specification of the SPI interface is 'sub optimal' (Euphemism for badly written). I had to look at the port test code to get it working. I did not want to use DMA as it complicates the code and is not required if you just want to send a byte. In fact I added the "wait before asserting cs" code because I noticed the chip select being very, very short high on my scope.To send 16 or 32 bits you just pump 2 or 4 bytes in the FIFO before you wait for it to be ready. (I think)
It's a shame we do not have GPIO19 and 20 as that gives access to the second SPI core which I wrote so of course it is much, much better