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by sheroy
Thu Apr 11, 2019 12:10 pm
Forum: Bare metal, Assembly language
Topic: When compiling for Pi3 in Arch32 enabling VFP
Replies: 12
Views: 3823

Re: When compiling for Pi3 in Arch32 enabling VFP

The actual fix is:

if you see the make file.. change it to...
ASMOPS = $(INCPATH) $(CPUOPS) $(libs)

It should fix the output initial post...

libs is a new variable... also the answer was posted on Fri Aug 31, 2018 4:39 pm

Edit -- Sorry got confused Thanks for pointing the date out!
by sheroy
Tue Jan 08, 2019 7:38 pm
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: DSI as GPIO
Replies: 10
Views: 1462

Re: DSI as GPIO

I also don't understand the connector on the DSI interface in some places shows GPIO 0 - 27 on that interface Because the documentation you mention is for the DPI interface, not the DSI. A different thing altogether. Ahh got it the converter board between the Pi and the display drives the display v...
by sheroy
Tue Jan 08, 2019 7:25 pm
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: DSI as GPIO
Replies: 10
Views: 1462

Re: DSI as GPIO

Hi I have tried SPI.... for a 12 bit adc… I requie some 16 clks… and am able to sample the adc at about 800 ksps in bare metal (MMU enabkes with cores at full frequency)… this translates to an SPI clock frequency of about 16MHz.... before errors creep in the SPI data.... The SPI clock divider is set...
by sheroy
Tue Jan 08, 2019 7:37 am
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: DSI as GPIO
Replies: 10
Views: 1462

Re: DSI as GPIO

Some more doubts... can the clk and data lanes be configured as outputs? or is it an hardwired input?
by sheroy
Mon Jan 07, 2019 7:58 pm
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: DSI as GPIO
Replies: 10
Views: 1462

Re: DSI as GPIO

This seems interesting.... I am right now talking about the CSI interface I would like to know if we can control the registers directly... ie data in and out... it looks like the CSI is based on the LVDS levels and thus could we hook up an LVDS based IO ADC to carry out the operation. I see 3 data p...
by sheroy
Sun Jan 06, 2019 11:07 pm
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: DSI as GPIO
Replies: 10
Views: 1462

Re: DSI as GPIO

In response to use the DSI or CSI interfaces for high speed GPIO in the RPi3B+ … in bare metal... What are the options? Is it possible to reconfigure the CSI and DSI pins and reroute them as GPIO's for high speed (> 40 MHz)? If so now?? I need about 12 high speed lines to interface an ADC. So I can ...
by sheroy
Sat Dec 15, 2018 1:45 pm
Forum: Bare metal, Assembly language
Topic: Building code with newlib-nano
Replies: 3
Views: 1328

[solved] Re: Building code with newlib-nano

It looks like after a bit of struggling I was able to fix it. When including libraries not in the default library path the -L option is used to include the new library such as NE10. But including this option apparently does not search the old library paths and this the linking process fails. I fixed...
by sheroy
Sat Dec 08, 2018 3:51 pm
Forum: Bare metal, Assembly language
Topic: Building code with newlib-nano
Replies: 3
Views: 1328

Re: Building code with newlib-nano

apparently I am unable to find libgcc from my compiler. Is it a part of the bare metal/embedded environment?

Edit - later I was able to link with libgcc but the errors yet exist. I think it is just a linker issue
by sheroy
Sat Dec 08, 2018 12:23 pm
Forum: Bare metal, Assembly language
Topic: Building code with newlib-nano
Replies: 3
Views: 1328

Building code with newlib-nano

I am using the arm bare metal toolchain (7 2018-q2-update - arm-none-eabi-*) to compile code that uses Newlib in the bare metal environment. I am unable to figure out the commands in the linker script to do the same. This is specific to use the NE10 library. The linker script gives errors such as: a...
by sheroy
Thu Nov 22, 2018 4:24 pm
Forum: Bare metal, Assembly language
Topic: How to carry out hardware cache maintenance on RPi3 AArch32
Replies: 0
Views: 1856

How to carry out hardware cache maintenance on RPi3 AArch32

To carry out hardware cache maintenance one needs to use the Snoop Control Unit (SCU) on the CortexA53. To access these signals, they are physical pins on the SoC (such as BROADCASTCACHEMAINT ). Is there any way via some mailbox interface to the GPU carry out such hardware cache maintenance operatio...
by sheroy
Wed Nov 21, 2018 10:40 pm
Forum: Bare metal, Assembly language
Topic: UART and Caching
Replies: 4
Views: 2990

Re: UART and Caching

This Helped me too for AARCH32!! I just had enabled MMU and caches, the code worked perfectly with either the data cache disabled or the MMU disabled. It did not work when both were enabled. In the code I was writing to the mailbox repeatedly to read the core temperature via the mailbox interface. O...
by sheroy
Sun Nov 11, 2018 9:28 pm
Forum: Bare metal, Assembly language
Topic: Able to get up only one core not others
Replies: 5
Views: 1634

[SOLVED] Re: Able to get up only one core not others

Hi LdB Solved IT!! I found out the cause. C function calls by default add lines for entry and return.... I added the attribute naked to the function whose address is being added in the core to enable function... so the definition of the function looks like void __attribute__((aligned(16), naked)) cO...
by sheroy
Fri Nov 09, 2018 7:00 pm
Forum: Bare metal, Assembly language
Topic: Able to get up only one core not others
Replies: 5
Views: 1634

Re: Able to get up only one core not others

Hi, I tried but not to any success. The core instantly crashes if I add a uart_puts or the led_blink test functions. These functions work well only on core 2 and core 0 where I boot from. Although the cores come up if these functions are removed! I tried adding a sev at the end of each core_enable f...
by sheroy
Thu Nov 08, 2018 9:29 pm
Forum: Bare metal, Assembly language
Topic: Able to get up only one core not others
Replies: 5
Views: 1634

Able to get up only one core not others

I am currently carrying out bare metal programming in c and I am able to get up only one core reliably. I have a main function that runs on core 0 initially (no kernel_old=1 in config file). I am able to move into SVC mode and initialize UART zero out BSS and start the main function. It prints out C...
by sheroy
Fri Aug 31, 2018 3:39 pm
Forum: Bare metal, Assembly language
Topic: When compiling for Pi3 in Arch32 enabling VFP
Replies: 12
Views: 3823

[solved] Re: When compiling for Pi3 in Arch32 enabling VFP

Sorry fixed it... my assembler options were not being updated
by sheroy
Fri Aug 31, 2018 2:37 pm
Forum: Bare metal, Assembly language
Topic: When compiling for Pi3 in Arch32 enabling VFP
Replies: 12
Views: 3823

Re: When compiling for Pi3 in Arch32 enabling VFP

I have not yet been able to figure out the problem. I have changed my compiler and have started using ARM DS5 to compile and use the makefile with a few modifications. The compiler is obtained from https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads and linked to the DS5 toolchain. ...
by sheroy
Tue Jul 17, 2018 8:19 pm
Forum: Bare metal, Assembly language
Topic: When compiling for Pi3 in Arch32 enabling VFP
Replies: 12
Views: 3823

Re: When compiling for Pi3 in Arch32 enabling VFP

last time the compiler flags were

-mfpu=neon-fp-armv8 -mfloat-abi=hard -march=armv8-a

It yet gave the same error.
by sheroy
Tue Jul 17, 2018 7:24 pm
Forum: Bare metal, Assembly language
Topic: When compiling for Pi3 in Arch32 enabling VFP
Replies: 12
Views: 3823

Re: When compiling for Pi3 in Arch32 enabling VFP

I tried I get the same error.
by sheroy
Fri Jul 13, 2018 10:36 pm
Forum: Bare metal, Assembly language
Topic: When compiling for Pi3 in Arch32 enabling VFP
Replies: 12
Views: 3823

When compiling for Pi3 in Arch32 enabling VFP

I am using arm-none-eabi-gcc (15:5.4.1+svn241155-1) 5.4.1 20160919 to compile. The instruction FMXR FPEXC, r0 (in my start.s file) gives the following error when compiling to enable VFP. Error: selected processor does not support `fmxr FPEXC,r0' in ARM mode my compiler flags are COPS = -Wall -nostdl...
by sheroy
Fri Jun 08, 2018 2:32 pm
Forum: Bare metal, Assembly language
Topic: Bare metal on raspberry pi 3 B+ not booting - finally working
Replies: 5
Views: 1851

Re: Bare metal on raspberry pi 3 B+ not booting - finally working

config.txt is not required to run bare metal on the pi, just need to have the right bootstrap and the right linker/entry address and possibly file name for the particular board. you should understand both how to override the defaults with config.txt but also use the defaults without. kernel8.img as...
by sheroy
Thu May 24, 2018 5:06 pm
Forum: Bare metal, Assembly language
Topic: Bare metal on raspberry pi 3 B+ not booting - finally working
Replies: 5
Views: 1851

Bare metal on raspberry pi 3 B+ not booting - finally working

I was trying bare metal to boot my kernel on the PI 3 B+. It was unable to boot. Disassembly of the elf file, assembly seemed right - nothing wrong. yet was unable to boot. Copied the files to kernel7.img and made a copy to kernel.img. Yet it did not seem to work. What worked was adding kernel=kerne...
by sheroy
Sat May 12, 2018 3:17 pm
Forum: Networking and servers
Topic: A simple fix for accessing raspberry pi by hostname from windows with samba
Replies: 0
Views: 901

A simple fix for accessing raspberry pi by hostname from windows with samba

I have spent a lot of time trying to configure access to the raspberry pi by the hostname through windows with programs like putty. Most of the topics I looked upon did not include the point below. To access the PPi by hostname.local just follow the steps below: Install samba sudo apt-get install sa...
by sheroy
Tue Nov 08, 2016 1:05 pm
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: Impedance of GPIO lines
Replies: 11
Views: 5276

Re: Impedance of GPIO lines

But what is the best impedance(on an average -- or as electrical engineers do by trial and error) to supply to the GPIO lines so that I can transfer data faster. I may be able to play with the drive strength to optimize the impedance of the source. I need to run the Sclk line at about 100 MHz... to ...
by sheroy
Sat Oct 29, 2016 12:41 pm
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: Impedance of GPIO lines
Replies: 11
Views: 5276

Impedance of GPIO lines

What is the impedance of the GPIO lines/tracks on the raspberry pi 3 and other models? Also does the SoC support digitally controlled impedance? What are the registers to tweak? Further what is the best performance(in terms of the eye diagram) that can be obtained with the GPIO. What is the best ter...

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