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by Schnoogle
Thu Dec 12, 2019 8:38 am
Forum: Bare metal, Assembly language
Topic: BX LR Seg Fault
Replies: 5
Views: 145

Re: BX LR Seg Fault

Hi, I'm definitely not an expert but from the code snippets you shared I assume you expect the link return address register (LR) to be "stacked". But it's not. So whenever you do a branch link call BL the contents of the LR register will be updated containing the last return address. But when you ca...
by Schnoogle
Fri Dec 06, 2019 8:39 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 486

Re: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called

Hey joncs,

thanks for the hint. This seems like a reasonable approach. I‘ll definitely give it a try... I was not aware of this possibility.

Regards
Schnoogle
by Schnoogle
Tue Dec 03, 2019 6:44 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 486

Re: Aarch64 - EL2 switch to EL3 - Exception Handler not called

Hey there, well it turned out that the default armv8stub.s does set the register SCR_EL to prevent any SMC call and makes it an undefined instruction (SMD flag set in SCR_EL3). So there seem to be only one way to deal with it using a config.txt to let my own kernel kick-off in EL3 and work from ther...
by Schnoogle
Tue Dec 03, 2019 9:49 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 RPi3 - MMU issue
Replies: 6
Views: 775

Re: Aarch64 RPi3 - MMU issue

Hi Valc,

thanks for your efforts. I guess this might have been the issue. After some refactoring of my code which might have eliminated this subtle bug as well the MMU is doing fine in aarch64 mode :)
Will mark the topic as solved.
by Schnoogle
Sun Nov 24, 2019 1:45 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 486

Re: Aarch64 - EL2 switch to EL3 - Exception Handler not called

If the first thing you want to do is to jump to EL3, i believe configuring it to start in EL3 is the best. Well at the moment my kernel targets to run in EL2 and as it shall act as kind of bootloader I‘d like to use EL3 as trampoline to switch to aarch32 EL2 in case a 32bit kernel is loaded and abl...
by Schnoogle
Sun Nov 24, 2019 11:24 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 486

Re: Aarch64 - EL2 switch to EL3 - Exception Handler not called

Hey,

yes my Pi is booting in EL2.
So would you propose to use config.txt to boot in EL3 to achieve what I‘m trying to do?

BR
Schnoogle
by Schnoogle
Sat Nov 23, 2019 11:56 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 486

[SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called

Hi there, I'm using my baremetal Pi in aarch64 mode. As far as I'm aware the initial mode (without any config.txt) would be aarch64 in EL2, right? What I try to achieve is to switch to EL3 in aarch64 and from there return to EL2 in aarch32 mode. This whole thing is working fine in QEMU but fails on ...
by Schnoogle
Sun Nov 03, 2019 5:22 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - RPi3 - Interrupts not triggering exception handler
Replies: 2
Views: 888

Re: Aarch64 - RPi3 - Interrupts not triggering exception handler

Hi there, well it seems that I was able to solve this on my own. I was missing to configure the IRQ routing in register HCR_EL2 . Even though my bare metal kernel keeps running in EL2 the interrups (e. from the timer) seem to be delivered only if this register is set to route any IRQ raised in any l...
by Schnoogle
Sun Nov 03, 2019 1:00 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - RPi3 - Interrupts not triggering exception handler
Replies: 2
Views: 888

Re: Aarch64 - RPi3 - Interrupts not triggering exception handler

Hi there,

while further investigating it seemed to be the case that interrupts are only delivered after switching from EL2 to EL1 which seems a bit of a surprise to me. Is there a register I need to write to enable interrupts also being delivered when the core is running in EL2 mode?
by Schnoogle
Thu Oct 31, 2019 3:50 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - RPi3 - Interrupts not triggering exception handler
Replies: 2
Views: 888

[SOLVED] Aarch64 - RPi3 - Interrupts not triggering exception handler

Hi there, I'm facing some trouble with interrupt handling in AARCH64 mode. I guess I set up everything - to my knowledge - but the interrupts does not trigger an exception call from my exception vector table. However, I can see there are pending interrupts based on the pending interrupt registers. W...
by Schnoogle
Thu Oct 31, 2019 2:34 pm
Forum: Bare metal, Assembly language
Topic: Inter CPU mailboxes
Replies: 1
Views: 355

Re: Inter CPU mailboxes

Hi there, you might want to checkout this document: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf It describes the core mailboxes available to achieve inter core communication. Those mailboxes also support interrupts to be triggered to ensure another core only...
by Schnoogle
Tue Oct 29, 2019 7:09 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 RPi3 - MMU issue
Replies: 6
Views: 775

Re: Aarch64 RPi3 - MMU issue

I'd gladly do that, although it's really primitive (just a prove of concept that 1:1 MMU mapping works at all, because other than for checking this feature out i did not find any use for it in my code) Well actually this is all what I’m after. I need the MMU to be set up to be able to use atomic op...
by Schnoogle
Tue Oct 29, 2019 2:57 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 RPi3 - MMU issue
Replies: 6
Views: 775

Re: Aarch64 RPi3 - MMU issue

Hi,

thx for the hint. I'll try to find my way with QEMU :)

In the meantime maybe you might be able to share the MMU entries you are using in case you also use 1:1 mapping with 2 levels only....

BR
Schnoogle
by Schnoogle
Sun Oct 27, 2019 8:59 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 RPi3 - MMU issue
Replies: 6
Views: 775

[SOLVED] Aarch64 RPi3 - MMU issue

Hi there, I do have a MMU issue I do not quite understand. I've read all the great and well written posts on that topic and I guess I did understand how to set the MMU up and I did this successfully with a 1:1 mapping. However, the memory access creates an Address size fault as soon as I try to acce...
by Schnoogle
Fri Oct 25, 2019 5:21 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] QEMU - AARCH64 RPi3 - DataAbort on address > 0x4000_0000
Replies: 1
Views: 614

Re: QEMU - AARCH64 RPi3 - DataAbort on address > 0x4000_0000

Hey there,

never mind and sorry for having bothered you :oops: . I figured it out. It was a MMU issue and the data abort indicated an translation fault at level 2. Sorry for the really beginner thing but I'm quite new to QEMU ;)

BR
Schnoogle
by Schnoogle
Fri Oct 25, 2019 10:38 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] QEMU - AARCH64 RPi3 - DataAbort on address > 0x4000_0000
Replies: 1
Views: 614

[SOLVED] QEMU - AARCH64 RPi3 - DataAbort on address > 0x4000_0000

Hi there, well I guess everything is in the title. While running QEMU on Windows with my bare metal aarch64 image I got data abort exceptions as soon as I try to access addresses > 0x4000_0000. This is odd as I'm not able to use the configuration registers located there :/ Any hint what kind of para...
by Schnoogle
Mon Oct 21, 2019 6:54 pm
Forum: Bare metal, Assembly language
Topic: [SLOVED] Aarch64 - "stp q0, q0, [x8, #224]" hangs my Pi3
Replies: 6
Views: 1604

Re: Aarch64 - "stp q0, q0, [x8, #224]" hangs my Pi3

Hi there, it turned out to really be an issue with the rust compiler. Adding a strict alignment flag solved the issue by generating code that complies to the required alignment rules... https://users.rust-lang.org/t/rust-compile-for-aarch64-target-creates-unaligned-stack-access/33842/5?u=2ndtalestud...
by Schnoogle
Mon Oct 21, 2019 8:37 am
Forum: Bare metal, Assembly language
Topic: [SLOVED] Aarch64 - "stp q0, q0, [x8, #224]" hangs my Pi3
Replies: 6
Views: 1604

Re: Aarch64 - "stp q0, q0, [x8, #224]" hangs my Pi3

So what are you doing to the stack that it is getting so upset about? Specifically I am querying are you inlining 64bit code assembler on a 32 bit version of linux which will have 8 byte stack alignment :-) Hey, well, interestingly I'm dooing complete bare-metal stuff in Aarch64. So there is no Lin...
by Schnoogle
Fri Oct 18, 2019 5:08 pm
Forum: Bare metal, Assembly language
Topic: [SLOVED] Aarch64 - "stp q0, q0, [x8, #224]" hangs my Pi3
Replies: 6
Views: 1604

Re: Aarch64 - "stp q0, q0, [x8, #224]" hangs my Pi3

I suppose you haven't enabled the MMU? It's an alignment problem. Hi, I checked with and without MMU beeing enabled. Some behaviour. What value is in x8? It should to be 16 byte aligned. Well actually this is the stackpointer. The compiler generates code like this: sub sp, sp, #0x130 add x8, sp, #0...
by Schnoogle
Fri Oct 18, 2019 12:59 pm
Forum: Bare metal, Assembly language
Topic: [SLOVED] Aarch64 - "stp q0, q0, [x8, #224]" hangs my Pi3
Replies: 6
Views: 1604

[SLOVED] Aarch64 - "stp q0, q0, [x8, #224]" hangs my Pi3

Hi there, while playing around with aarch64 mode I've seen my Raspberry Pi hangs at a specific instruction. The compiler is generating: stp q0, q0, [x8, #224] and I've proven with handwritten code at a specific known location that this code hangs my Pi. Does anyone could point me into a direction wh...
by Schnoogle
Wed Oct 16, 2019 2:18 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - how many cores are kicked off in the first place ?
Replies: 5
Views: 1380

Re: Aarch64 - how many cores are kicked off in the first place ?

Hi,

thanks a ton for the confirmation and the great and detailed explanation!

Regards
Schnoogle
by Schnoogle
Wed Oct 16, 2019 9:12 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - how many cores are kicked off in the first place ?
Replies: 5
Views: 1380

Re: Aarch64 - how many cores are kicked off in the first place ?

Hi, thx. for the response. Sorry for my ignorance, but just to "double" check. The armstub8.S you provided is some sort of code that is expected to be part of my own bare metal kernel or this is the code that broadcom provides in bootcode.bin / start.elf which is run as soon the PI get's powered up?...
by Schnoogle
Wed Oct 16, 2019 9:00 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] Clear bss section before or after setting up the MMU?
Replies: 4
Views: 1219

Re: Clear bss section before or after setting up the MMU?

Hey,

thanks for the detailed explanation. I guess I now got the point :)

BR
Schnoogle
by Schnoogle
Tue Oct 15, 2019 2:30 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Clear bss section before or after setting up the MMU?
Replies: 4
Views: 1219

Re: Clear bss section before or after setting up the MMU?

Hi, thanks for the response and the provided link. However, I’m concerned about the address translation of MMU if it is not a 1:1 mapping. So if bss is cleared before MMU Setup the memory access to bss section after MMU Setup might result in a different physical address which is not initialized.? As...
by Schnoogle
Tue Oct 15, 2019 12:36 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Clear bss section before or after setting up the MMU?
Replies: 4
Views: 1219

[SOLVED] Clear bss section before or after setting up the MMU?

Hi there,

might be a stupid question, but when to initialize the bss section during the boot sequence of a bare metal kernel. Should it be done before or after the MMU has been setup?

Thanks in advance for any hint.

BR
Schnoogle

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