Go to advanced search

by btauro
Sun Apr 29, 2018 2:52 am
Forum: Bare metal, Assembly language
Topic: Virtual Memory Error while writing memory in EL0
Replies: 0
Views: 383

Virtual Memory Error while writing memory in EL0

Hi, I have both ttbr0 and ttbr1 point to the same page tables for now.I have set up the page tables in such a way that i can write memory in EL0 but for some reason this is not working.It gives me the following errors. Can you tell me what are the flags which mioght cause this error.Is there some pa...
by btauro
Thu Apr 19, 2018 6:32 am
Forum: Bare metal, Assembly language
Topic: Setting page tables with ttbr1_el1 in RPI3
Replies: 2
Views: 769

Setting page tables with ttbr1_el1 in RPI3

Hi, I have successfully set 64 KB page tables using ttbr0_el1. but whenever i try setting the page tables using ttbr1_el1 it stops working. I tried starting the linker from 0xFFFF000000000000 but even this did not help i set the attributes correctly enabling ttbr_el1 page walks I enable the page tab...
by btauro
Fri Apr 13, 2018 4:42 pm
Forum: Bare metal, Assembly language
Topic: Multithreading in RPI 3 64 bit
Replies: 1
Views: 917

Multithreading in RPI 3 64 bit

Hi, For Now I have all cores parked using WFI how do i wakeup these cores .I am using 64 bit for the bare metal os. I want to implement threads on The RPI3 Bare OS.So i have looked through the ldrex,strexeq . Apart from the exclusive access are there any hardware support available for threads in RPI...
by btauro
Wed Feb 21, 2018 1:21 am
Forum: Bare metal, Assembly language
Topic: Memory address range for ARM in RPI3?
Replies: 8
Views: 2435

Re: Memory address range for ARM in RPI3?

Thank you so much for all the support :D
by btauro
Tue Feb 20, 2018 7:44 pm
Forum: Bare metal, Assembly language
Topic: Memory address range for ARM in RPI3?
Replies: 8
Views: 2435

Re: Memory address range for ARM in RPI3?

Thank you Every1 for your valuable support I got the memory changed by adding these two particular files as suggested above with Extended GPU mode 1]fixup_x.dat 2]start_x.elf And having config text set to gpu_mem=64 start_x=1 I had Arm start from 00000000 to 3B000000 which is 944 MB GPU is 64 MB and...
by btauro
Fri Feb 16, 2018 8:51 pm
Forum: Bare metal, Assembly language
Topic: Memory address range for ARM in RPI3?
Replies: 8
Views: 2435

Re: Memory address range for ARM in RPI3?

hi, Thanks for helping me For Arm Start=0000000 size 08000000 which is only 128 MB for gpu: start =08000000 size= 08000000 which again is 128MB i tried changing this using config text by setting the parameter gpu_mem=64 but still it showed me th above results. Are these values correct how can i chan...
by btauro
Fri Feb 16, 2018 7:38 am
Forum: Bare metal, Assembly language
Topic: Memory address range for ARM in RPI3?
Replies: 8
Views: 2435

Memory address range for ARM in RPI3?

Hi, I know that ARM has 880 MB and GPU about 120 MB which can be changed . But while writing translation tables i say few implementations where the ARM was given only 512 MB and GPU 64 MB? Does the ARM have only 512 MB memory for translation and remaining for IO and device Memory and GPU (VCU)? How ...
by btauro
Fri Feb 16, 2018 7:30 am
Forum: Bare metal, Assembly language
Topic: Translation Table 64 kb
Replies: 2
Views: 919

Re: Translation Table 64 kb

Thank you for helping me out :D
by btauro
Sat Feb 10, 2018 8:00 pm
Forum: Bare metal, Assembly language
Topic: Synchronous Exception Synchronous exception: Data abort, same EL, Address size fault at level 1:
Replies: 3
Views: 1211

Re: Synchronous Exception Synchronous exception: Data abort, same EL, Address size fault at level 1:

Thank you so much still looking into it but for some reason a parameter in level 3 table descriptor that is the ignored field if commented it works fine .I am not sure why. struct TARMV8MMU_LEVEL3_PAGE_DESCRIPTOR { u64 Value11 : 2, // set to 3 //LowerAttributes : 10, AttrIndx : 3, // [2:0], see MAIR...
by btauro
Sat Feb 10, 2018 7:58 pm
Forum: Bare metal, Assembly language
Topic: Translation Table 64 kb
Replies: 2
Views: 919

Translation Table 64 kb

I have been trying to set up page tables using 64 KB page size with three levels.However for some reason if i have my ttbr0 point to level 2 it works just as in circle 64 but if i create level1 and have ttbr0 point to level 1 it does not.I have gone through the system registers but i did not find an...
by btauro
Wed Feb 07, 2018 5:54 am
Forum: Bare metal, Assembly language
Topic: Synchronous Exception Synchronous exception: Data abort, same EL, Address size fault at level 1:
Replies: 3
Views: 1211

Synchronous Exception Synchronous exception: Data abort, same EL, Address size fault at level 1:

Hi, I have been trying to initialise circle 64 MMU but so far when i try creating the translation tables i get this Synchronous exception: Data abort, same EL, Address size fault at level 1: ESR_EL1 00000025og96000061 ELR_EL1 00000000000003C4 SPSR_EL1 0000000000083C18 FAR_EL1 0000000000083C20 X30 00...
by btauro
Wed Jan 31, 2018 8:54 pm
Forum: Bare metal, Assembly language
Topic: Secure state and Non Secure state in MMU
Replies: 1
Views: 585

Secure state and Non Secure state in MMU

Hi, I am trying to figure out the MMU for RPI 3 but the secure state and non secure state is where i am stuck.On help on this forum i was guided to this particular link https://www.arm.com/products/security-on-arm/trustzone. Can any one help me with how does the MMU change or the address change when...
by btauro
Sun Jan 28, 2018 12:22 am
Forum: Bare metal, Assembly language
Topic: Secure state and non secure state in Rpi3
Replies: 4
Views: 1333

Re: Secure state and non secure state in Rpi3

Thank you for helping me out So according to https://www.arm.com/products/security-on-arm/trustzone i Each physical processor core has two virtual cores: one considered secure and the other non-secure and a robust mechanism is provided to context switch between them (Secure Monitor exception So does...
by btauro
Sat Jan 27, 2018 11:32 pm
Forum: Bare metal, Assembly language
Topic: Secure state and non secure state in Rpi3
Replies: 4
Views: 1333

Secure state and non secure state in Rpi3

Hi, I know secure state is something do with secure physical address space and non secure state is nonsecure physical address space according to ARMv8. Secure state u can look up both secure and non secure address Non Secure State -u Can look only on non secure address on Further lookup i know this ...
by btauro
Fri Jan 26, 2018 1:54 am
Forum: Bare metal, Assembly language
Topic: Exception Table in Raspberry pi 3 64 bit
Replies: 2
Views: 700

Re: Exception Table in Raspberry pi 3 64 bit

Yes i already have taken an os course 2 years ago but now have passion to build one .And your tutorials have really been a blessing in disguise for me.


Thank you so much,
by btauro
Tue Jan 23, 2018 6:13 pm
Forum: Bare metal, Assembly language
Topic: Exception Table in Raspberry pi 3 64 bit
Replies: 2
Views: 700

Exception Table in Raspberry pi 3 64 bit

Hi, Do we need to have exception table in raspberry pi3 64 in this format or is there some other way to build the exception table reset_handler undefined_handler swi_handler prefetch_handler data_handler unused_handler irq_handler fiq_handler 1. For Interrupt handling having an exception table inclu...
by btauro
Sun Jan 21, 2018 2:10 am
Forum: Bare metal, Assembly language
Topic: Switch between exception level 3 to exception level 2
Replies: 4
Views: 1271

Re: Switch between exception level 3 to exception level 2

Finally got it working by adding these two lines to switch from el2 to el1 //set up el1 toAARCH64 mov x1,#0x80000000 msr hcr_el2,x1 But i would like to know why in oder to switch from EL2 to EL1 why do we need to set Hypervisor Configuration Register on Raspberry Pi 3. I have gone through the docume...
by btauro
Sat Jan 20, 2018 6:19 pm
Forum: Bare metal, Assembly language
Topic: Switch between exception level 3 to exception level 2
Replies: 4
Views: 1271

Re: Switch between exception level 3 to exception level 2

Hey, Yes you are right.in my config.txt the lines below cause my Exception Level to go to 00000003 kernel_old=1 disable_commandline_tags=1 Thank you so much for helping me. But I still did not get serial output. For some reason the change from execution level 2 to level 1 code is not working resulti...
by btauro
Sat Jan 20, 2018 6:13 am
Forum: Bare metal, Assembly language
Topic: Switch between exception level 3 to exception level 2
Replies: 4
Views: 1271

Switch between exception level 3 to exception level 2

Hello, I have been trying an rpi3 Exception level tutorial from https://github.com/bztsrc/raspi3-tutorial/blob/master/0F_executionlevel/ . But some how in the the assembly code start.S switching from El level 2 to El level 1 does not work and results in no serial output in Minicom And wen i print my...
by btauro
Thu Jan 18, 2018 4:52 am
Forum: Bare metal, Assembly language
Topic: Difference between Interrupts in x86 and Exceptions in Arm
Replies: 5
Views: 1328

Re: Difference between Interrupts in x86 and Exceptions in Arm

Thank you so much for helping me out.
i am very grateful to this forum get to learn a lot

Thanks
by btauro
Wed Jan 17, 2018 4:43 am
Forum: Bare metal, Assembly language
Topic: Difference between Interrupts in x86 and Exceptions in Arm
Replies: 5
Views: 1328

Re: Difference between Interrupts in x86 and Exceptions in Arm

Thank you for helping me out. Honestly i am just a baby right now in both x86 and ARM world but I always had a passion to build an OS .So I have decided to build at least a minimal kernel for raspberry pi3. So basically yes I have worked only in real mode. I still have few questions which i do not k...
by btauro
Wed Jan 17, 2018 2:22 am
Forum: Bare metal, Assembly language
Topic: Difference between Interrupts in x86 and Exceptions in Arm
Replies: 5
Views: 1328

Difference between Interrupts in x86 and Exceptions in Arm

Hi, I am having a tough time to understand what is exception levels in ARMv8 and its significance when building Page Tables and Interrupt handling.I know we have 4 levels.EL0,EL1,EL2,El3. Is Exception similar to Interrupt handling in X86 . And while building a kernel in ARMv8-A 64 bit do we have to ...
by btauro
Tue Jan 16, 2018 8:33 am
Forum: Bare metal, Assembly language
Topic: Do we have Global descriptor Table in ARM for raspberry pi3
Replies: 1
Views: 680

Do we have Global descriptor Table in ARM for raspberry pi3

Hi,

I would like to know do we need to implement GDT in ARM before building an Interrupt Table?
Do we have the concept of Segmentation in ARM?
Are there any reference links regarding how we we build Interrupt Table and handlers in ARM?

Go to advanced search