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by AALLeeXXX
Wed Jan 16, 2019 4:10 pm
Forum: Bare metal, Assembly language
Topic: EL switching
Replies: 7
Views: 1528

Re: EL switching

Hello Bzt, Thank you for your highlights and guidance. I finally found out what happened.. and this was not related to EL change directly, but instead, I triggered a trapped access to SIMD and FP features which I did not catch properly ! Thus even I entered in EL1, I could not 'see' it... I did not ...
by AALLeeXXX
Thu Jan 10, 2019 4:48 pm
Forum: Bare metal, Assembly language
Topic: EL switching
Replies: 7
Views: 1528

EL switching

Hello I still struggle to dynamically change the EL with my PI3 in AARCH64. (If I do it at boot from reset, I can enter EL2 or EL1 successfully, no pb here). I start the ARM in 64bits at EL3 and keep it at this level. Then I want to dynamically switch to EL2. So, I call HVC #0. This triggers the Syn...
by AALLeeXXX
Tue Nov 20, 2018 12:26 pm
Forum: Bare metal, Assembly language
Topic: SP_EL3 ?
Replies: 11
Views: 3187

Re: SP_EL3 ?

Thank you all for your reply’, it’s clear now, naming conventions confused me. About LdB concern, sorry it might be naive, but in arm v8 does IRQ state have its own stack ? It does in arm v7, but I did not understand that from the armv8 docs. It would use either current EL stack or stack of EL0 depe...
by AALLeeXXX
Tue Nov 20, 2018 12:26 pm
Forum: Bare metal, Assembly language
Topic: SP_EL3 ?
Replies: 11
Views: 3187

Re: SP_EL3 ?

Thank you all for your reply’, it’s clear now, naming conventions confused me. About LdB concern, sorry it might be naive, but in arm v8 does IRQ state have its own stack ? It does in arm v7, but I did not understand that from the armv8 docs. It would use either current EL stack or stack of EL0 depe...
by AALLeeXXX
Mon Nov 19, 2018 4:11 pm
Forum: Bare metal, Assembly language
Topic: SP_EL3 ?
Replies: 11
Views: 3187

SP_EL3 ?

Hello, Quite basic question, but does SP_EL3 exist in PI3 ? Assembler (Linaro toolchain) rejects ant access to it. Others (sp_el2/1/0) are fine but not that one. What did I overlooked ? The arch ref man is also unclear about this one, access section is empty. Would it be simple SP when in EL3 and hi...
by AALLeeXXX
Mon Oct 29, 2018 11:58 am
Forum: Bare metal, Assembly language
Topic: Masking Sync exceptions on PI3
Replies: 2
Views: 1607

Re: Masking Sync exceptions on PI3

Yes this in indeed the observed behavior. I just wondered whether this sync exception could be masked ? I could not find any mask for it, and no statement of the contrary either. I might have overlooked it.
Thanks
by AALLeeXXX
Sat Oct 27, 2018 3:07 pm
Forum: Bare metal, Assembly language
Topic: Masking Sync exceptions on PI3
Replies: 2
Views: 1607

Masking Sync exceptions on PI3

Hello, I'm new to the PI3 and try now playing with exceptions. I start the PI in EL3 / aarch64 and keep in this state for my tests. Then I execute a SVC. This triggers an exception, Synchronous one. I have one concern here: at start-up DAIF masks A, I and F and only keeps D unmasked. Is it then expe...
by AALLeeXXX
Mon Jul 23, 2018 1:25 pm
Forum: Bare metal, Assembly language
Topic: RPi OS development tutorial
Replies: 5
Views: 5488

Re: RPi OS development tutorial

Hello Bzt, Thank you for this clarification. This is quite clear about the target software we build with the toolchain. But then, since I'm using the freestanding toolchain (it's also indicated in the gcc options), why is this library requested here ? Is it required to be linked in the target softwa...
by AALLeeXXX
Sun Jul 22, 2018 2:55 pm
Forum: Bare metal, Assembly language
Topic: RPi OS development tutorial
Replies: 5
Views: 5488

Re: RPi OS development tutorial

Hello, Thank you very much for this great tuto ! I'm trying it now and have some concern related to the toolchains. I successfully compiled the first example, but I'm not clear here about the tool chain. I installed this gcc-aarch64-linux-gnu package. But naming convention seems different and I cann...
by AALLeeXXX
Sat Mar 17, 2018 3:18 pm
Forum: Bare metal, Assembly language
Topic: Executing code on a particular core (RPi 2)
Replies: 23
Views: 6503

Re: Executing code on a particular core (RPi 2)

Thank you all for your inputs. It's more clear now and I have better directions to search now.
by AALLeeXXX
Thu Mar 15, 2018 4:22 pm
Forum: Bare metal, Assembly language
Topic: Executing code on a particular core (RPi 2)
Replies: 23
Views: 6503

Re: Executing code on a particular core (RPi 2)

Hello LdB, Thanks for the reply. Not sure whet you call a spin loop. I guess a endless loop with an exit condition, correct ? About that doc, I knew it already, but it does not give the mailbox allocation. I want to know the usage of each of them. This doc just states they are all the same and progr...
by AALLeeXXX
Wed Mar 14, 2018 1:58 pm
Forum: Bare metal, Assembly language
Topic: Executing code on a particular core (RPi 2)
Replies: 23
Views: 6503

Re: Executing code on a particular core (RPi 2)

Hello,

Just in case some still read this topic ... We discover here how to start a core. but... how to stop a core ??

I cannot find any document explaining the mailbox allocation , eg mailbox 3 of each core as a start address.. did I overlook soemething ?

Thanks
by AALLeeXXX
Sun Dec 17, 2017 7:48 am
Forum: Bare metal, Assembly language
Topic: CP15SDISABLE, where is it, how to set it ?
Replies: 1
Views: 527

CP15SDISABLE, where is it, how to set it ?

Hello hello,

From the ARM ARM I understand that signal above is connected to an input. But I cannot find it in the PI documentation. Did I overlook at some materials ? Do you know where is it ‘connected’ ?

Thanks for any hint..
by AALLeeXXX
Wed Nov 29, 2017 5:12 pm
Forum: Bare metal, Assembly language
Topic: Unique SP for both secure and non-secure modes ?
Replies: 1
Views: 510

Re: Unique SP for both secure and non-secure modes ?

In case some would have the same question, no, SP are common - not banked - between secure and non secure state.
by AALLeeXXX
Wed Nov 22, 2017 3:35 pm
Forum: Bare metal, Assembly language
Topic: Unique SP for both secure and non-secure modes ?
Replies: 1
Views: 510

Unique SP for both secure and non-secure modes ?

Hello, Not sure at all about above statement. I know each mode has its own SP, but for a given PL1 mode, does it share a unique SP when in secure state and non-secure state ? Do secure SVC and non-secure SVC use the same stack ? In docs, SP does not appear as "banked" in secure and non-secure modes,...
by AALLeeXXX
Sat Nov 18, 2017 1:47 am
Forum: Bare metal, Assembly language
Topic: as options for security extensions (RPI2)
Replies: 4
Views: 948

Re: as options for security extensions (RPI2)

Ok, sorry, i confused (and that made no sense)

Thanks again :)
by AALLeeXXX
Fri Nov 17, 2017 1:29 pm
Forum: Bare metal, Assembly language
Topic: as options for security extensions (RPI2)
Replies: 4
Views: 948

Re: as options for security extensions (RPI2)

To get a banked core register from a different bank to what you are currently in you have to use mrs Oh, I was not aware of that, thanks for that hint ! Fixed for now. One point however... does really as knows in which mode the code runs ?? Also, even it would, my code snippet is supposed to be (no...
by AALLeeXXX
Thu Nov 16, 2017 4:12 pm
Forum: Bare metal, Assembly language
Topic: as options for security extensions (RPI2)
Replies: 4
Views: 948

as options for security extensions (RPI2)

Hello all, I think I overlooked a (supposed to be) basic option but I cannot assemble an assembler file that contains the LR_mon register. I expected this would be enabled by settings the options for security extentions but still cannot get it... arm-none-eabi-as --warn --fatal-warnings -I src -mcpu...
by AALLeeXXX
Tue Oct 24, 2017 11:25 pm
Forum: Bare metal, Assembly language
Topic: RPI2 - Booting from 0 with kernel_old=1
Replies: 4
Views: 1174

Re: RPI2 - Booting from 0 with kernel_old=1

Hello LdB, You’re right and I found your samples of multi core startup - I will dive there later. But for now, do I need the FPU in it when I even don’t use it ? Of that code I understand that one core 0 is started and others are pending on wfi. Core 0 SP is set later at the startup of “the applicat...
by AALLeeXXX
Tue Oct 24, 2017 2:50 pm
Forum: Bare metal, Assembly language
Topic: RPI2 - Booting from 0 with kernel_old=1
Replies: 4
Views: 1174

RPI2 - Booting from 0 with kernel_old=1

Hello I'm trying to boot my PI2 from 0 instead of 0x8000 with config file option kernel_old=1. I took the foundation's stub file as a starting point, armstub7.S. I made some changes in it in order to keep in secure mode when starting the "application" - here again I just borrowed David Welch's bootl...
by AALLeeXXX
Fri Sep 01, 2017 3:24 pm
Forum: Bare metal, Assembly language
Topic: gcc options for virtualisation ?
Replies: 6
Views: 1517

Re: gcc options for virtualisation ?

Oh, ok, confirmed !
arm-none-eabi-gcc -c -O0 -mfpu=neon-vfpv4 -mfloat-abi=hard -march=armv7ve -mtune=cortex-a7 -g -nostartfiles -Wa,-acdghln=obj/pishell.lst -DRPI2 -o obj/pishell.o src/pishell.c

Works fine with the immediate value as argument, I though it was optional.

Thanks !!
by AALLeeXXX
Fri Sep 01, 2017 2:17 pm
Forum: Bare metal, Assembly language
Topic: gcc options for virtualisation ?
Replies: 6
Views: 1517

Re: gcc options for virtualisation ?

#define __HVC(imm16) __inst_arm_thumb32( \ 0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F), \ 0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \ ) Wooo, indeed !! Seems however this code is pretty ld now, 2012... maybe gcc did not support virtualisation instructions ? But the...
by AALLeeXXX
Fri Sep 01, 2017 2:07 pm
Forum: Bare metal, Assembly language
Topic: gcc options for virtualisation ?
Replies: 6
Views: 1517

Re: gcc options for virtualisation ?

Hello Thanks for the reply. Well, indeed in the tools chain I was using, a pretty old one (gcc-arm-none-eabi-4_7-2013q3) the armv7ve was not available. Then I changed to a recent toolchain gcc-arm-none-eabi-6-2017-q2-update... but I don't get any better result with either one or other options set: a...
by AALLeeXXX
Wed Aug 30, 2017 1:56 pm
Forum: Bare metal, Assembly language
Topic: gcc options for virtualisation ?
Replies: 6
Views: 1517

gcc options for virtualisation ?

Hello everybody, I'm trying to embed a HVC instruction in my C source directly, with a statement asm ("hvc"); but gcc reports the following error: arm-none-eabi-gcc -c -O0 -mfpu=neon-vfpv4 -mfloat-abi=hard -march=armv7-a -mtune=cortex-a7 -g -nostartfiles -Wa,-acdghln=obj/pishell.lst -DRPI2 -o obj/pi...
by AALLeeXXX
Sun Aug 20, 2017 1:24 pm
Forum: Bare metal, Assembly language
Topic: SVC argument
Replies: 11
Views: 2598

Re: SVC argument

I found that strange and have just looked up the docs for the Cortex M3. Whilst the M3 pushes some registers onto the stack automatically for you when entering SVC, the usage of the number is exactly the same as other ARM chips in that the processor ignores it and leaves it up to you to obtain it f...

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